Pigeon Point BMR-A2F-VPX Reference Design

1 Pigeon Point BMR-A2F-VPX Reference Design Page 1 / 8 PRODUCT BRIEF Pigeon Point BMR-A2F-VPX Reference Design Board Management Reference Design for VPX and VITA May 16, 2018 nVent Schroff GmbH All nVent brands and logos are the property of nVent or its affiliated companies worldwide. nVent reserves the right to change information without prior notification. Pigeon Point BMR-A2F-VPX Reference Design Page 2 / 8 The BMR-A2F-VPX des i gn i s one of a s eri es of Pi geon Poi nt Board Management Reference des i gns . Thi s member of the s eri es provi des an Intel l i gent Pl atform Management Control l er (IPMC) for VPX and VITA and i s bas ed on the SmartFus i on i ntel li gent mi xed-s ignal FPGA from Mi cros emi Corporation. Thi s Reference des i gn i s del i vered i n a Pi geon Poi nt Board Management Starter Ki t (whi ch i s detai l ed i n a s eparate Product Bri ef).

2 The ki t i ncl udes : A SmartFus i on FPGA des i gn that i mpl ements the core of an IPMC, worki ng wi th the Cortex-M3 ARM proces s or and s upporti ng peri pherals i n the mi crocontroller s ubs ystem (MSS). Thi s des i gn i s ready to be adapted for your VPX pl ug-i n modul e or other i ntel l i gent Fi el d Repl aceabl e Uni t (FRU), s uch as a fan tray. Schemati cs for a corres ponding IPMC s ubs ys tem, ready for i ntegrati on i nto the s chemati c for your board, wi th adaptati on as neces s ary Fi rmware for that s ubs ys tem, del i vered i n s ource form and wi th devel opment tool s ready for s i mpl e and qui ck adaptation to your requi rements Deri ved from wi del y us ed BMR-A2F-ATCA product, i nheri ti ng s ubs tanti al benefi ts from more than a decade of fi el d us e and i nteroperabi l ity tes ti ng for BMR-bas ed management control l ers One-s top s upport from nVent for s chemati cs , fi rmware and s oftware us ed i n devel opi ng and del i veri ng your Pi geon Poi nt BMR-bas ed IPMC Compl ementary s upport from Mi cros emi for the FPGA des i gn.

3 I ncl udi ng adaptations to meet the s peci fi c needs of your board The photo i n the next col umn s hows the core of a BMR-A2F-VPX IPMC. The acti ve components are: The A2F200 i ntel l i gent mi xed-s i gnal FPGA. Dual IPMB buffers to i s ol ate the IPMC from dual redundant Sys tem IPMB i mpl emented on the backpl ane. An external os ci l lator to provi de the operati ng frequency. Specification compliant and interoperability tested ANSI/VITA , Sys tem Management on VPX PICMG , the Fi rmware Upgrade s peci fi cation and , the LAN-attached IPM Control l er and DHCP-as signed Pl atform Management Parameters s peci ficati ons (revi s i ons and , res pecti vel y) IPMI , document revi s i on and the rel evant s ubs et of IPMI , document revi s i on , pl us rel evant errata and IPMI compl i ance i ncludes s upport for Internet Protocol vers i on 6 (IPv6)1 Benefi ts from thorough tes ti ng i n ATCA context wi th other management components at PICMG TCA-IWs (Interoperabi l ity Works hops )

4 VPX-s pecific VSO event Full support for core hardware requirements 32-bi t Cortex-M3 operati ng at 80 MHz for IPMC fi rmware executi on VITA and IPMI-aware moni tori ng of des i gnated SmartFus i on analog s ens ors vi a SmartFusion s programmable analog s ubs ys tem, wi thout us i ng Cortex-M3 proces s or cycles Supports A2F200/500 vari ants, i ncluding CS288, FG256 and FG484 packages Payl oad vol tage moni tori ng (i ncluding the vari ous power s uppl y rails that can be del i vered from a VPX backpl ane) 1 IPv6 support is not present in ANSI/VITA ; it was added to the ATCA HPM subsystem after VITA was modeled on that subsystem. Any future IPv6 support in VITA will likely be modeled on the ATCA support, as well. Pigeon Point BMR-A2F-VPX Reference Design Page 3 / 8 Thermal s ens ors (i nternal SmartFus ion temperature moni tors wi th external bi pol ar trans i stors and/or external DS75 di gital s ens ors ) bl e di rect LAN attachment i nterface or s i deband LAN attachment i nterface i mpl emented vi a ei ther non-propri etary Network Control l er Si deband Interface (NC-SI) or Intel-propri etary SMBus s i deband i nterface to payl oad NCs , capable of handl i ng IPMI over LAN (i ncl uding Seri al over LAN, upgrades , IPMB trace acces s and other i ant extens i ons )

5 Dual redundant Sys tem IPMB, wi th VITA i ant opti on to us e j us t IPMB-A, wi thout IPMB-B Geographi c addres s detecti on from backpl ane FRU LED management Payl oad power s uppl y controls (mul tiple vol tage l evel s ), wi th opti onal pers i stence acros s IPMC res ets Opti onal l ocal Sys tem Event Log (SEL) Opti onal i nfrastructure for non-i ntel l igent Rear Trans i ti on Modul es UART- or LPC/KCS-bas ed payl oad i nterface UART-bas ed s eri al debug i nterface Small footprint Core IPMC can fi t i n the fol l owi ng package-dependent footpri nts : 25mm x 31mm (CS288), x 34mm (FG256) or 34mm x 44mm (FG484) Optional support for special purpose functionality Tel co (dry contact) al arm management Chas s is FRU Informati on SEEPROM acces s Programmable analog subsystem eliminates Cortex-M3 processor cycles for monitoring analog sensors Wi thi n Anal og Compute Engi ne, Sampl e Sequenci ng Engi ne (SEE) moni tors up to 32 SmartFus i on analog i nputs, wi th Pos t Proces s i ng Engi ne (PPE)

6 Confi gurable to do IPMI-compati ble proces sing of the readi ngs , i ncl uding thres hol d detecti on Onl y readi ngs that cros s thres hol ds res ult i n i nterrupts to the Cortex-M3 proces s or Ful l y confi gurable s ens or s ampl ing and thres hol d detai l s, us i ng Mi crosemi MSS Confi gurator tool Instance-specific information storage in SmartFusion FlashROM Opti onal s upport i n fi rmware for retri evi ng i ns tance-s pecific i nformation (s uch as a modul e s eri al number) from s peci al 1 Kbi t Fl as hROM area that can onl y be wri tten vi a JTAG Coordi nates wi th Mi cros emi tool facilities to al l ow automati c s erializi ng of s ucces sivel y programmed SmartFus i on devi ces Adaptable and extendable FPGA Design Ini ti al FPGA des i gn provi ded i n s everal variants ( for di fferent package s i zes )

7 , can be us ed di rectl y or modi fi ed Potenti al modi fi cati ons i nclude addi ng or removi ng Mi cros emi IP bl ocks, addi ng custom l ogi c and/or IP bl ocks, changing devi ce pi n as s i gnments , i f neces s ary Comprehensive, readily adaptable firmware Al l mandatory and many opti onal IPMI/VPX commands s upported over Sys tem IPMB Numerous Pi geon Poi nt extens i on commands , pri mari ly us ed over the payl oad and s erial debug i nterfaces Payl oad alert noti fi cations over payl oad i nterface for s ens or events and recei pt of res et/s hutdown commands PICMG fi rmware upgrade s upport Si mpl e but hi ghl y fl exi ble configuration of fi rmware features Pigeon Point BMR-A2F-VPX Reference Design Page 4 / 8 Sophisticated, support for firmware upgrades Fi rmware upgrades over any IPMI i nterface to the IPMC, wi th redundant copi es and automati c fal l back after fai led upgrade IPMC i s ful l y functi onal during upgrade Bootl oader can be upgraded wi thout us i ng JTAG Framework for managi ng fi rmware upgrades that i ncl ude changes i n data s tructures that are pres erved acros s IPMC resets to el i mi nate di s rupti ve upgrades IPMC FRU Informati on i mpl emented as addi ti onal component.

8 Al l owi ng FRU Informati on upgrades i ndependentl y of fi rmware Opti onal capability to upgrade FPGA des i gn wi thout us i ng JTAG Opti onal upgrades vi a IPMI over LAN i nterface Open s ource i pmi tool s upplied as upgrade agent compl i ance means that any compl i ant upgrade agent can upgrade any compl i ant IPMC Optional support for non-intelligent Rear Transition Modules (RTM) Incl udes s pecific hardware and fi rmware s upport for i nterface between front board and RTM Al l ows compl i ance wi th VITA requi rements regardi ng how an RTM i s repres ented by the IPMC Choice of serial interface protocols (SIPL variants) supported via UARTs to payload processor and serial debug interface SIPL-TM, bas ed on IPMI-defi ned Termi nal Mode of the Seri al /Modem Interface, SIPL-BM bas ed on IPMI-defi ned Bas i c Mode, Ei ther protocol s el ectable i ndi vidually for ei ther s eri al i nterface SIPL-TM: human-ori ented and ASCII-bas ed, i ntended pri marily for the s eri al debug i nterface SIPL-BM.

9 Machi ne-ori ented and bi nary-based, i ntended pri mari ly for the UART-bas ed payl oad i nterface Both protocol s us e encoded forms of raw IPMI mes s ages , whi ch are handl ed by the IPMC es s enti al ly l ike IPMB mes s ages Optional use of LPC/KCS for payload interface2 Enabl ed i n l i eu of UART-bas ed payl oad i nterface Bas ed on IPMI-defi ned KCS vari ant of IPMI Sys tem Interface, i mpl emented over LPC i n Mi cros emi CoreLPC Faci l itates us e of exi s ti ng IPMI s oftware on payl oad proces sor, whi ch often i nterfaces wi th management control l er vi a KCS Optional Simple Network Stack Ethernet l ayer, i ncl uding dri vers for SmartFus i on Ethernet MAC and for SMBus s i deband l i nk to s el ected Intel NCs Internet Protocol (IP) l ayer, whi ch cooperates wi th ARP modul e to res ol ve IP addres s to MAC addres s es IP-bas ed protocol l ayer, i ncluding UDP and ICMP Provi des foundati on for applicati on protocol s, s uch as RMCP and RMCP+ Optional IPMI over LAN Pri mary cl ient of s i mpl e network s tack IPMI compl i ant i mpl ementati on of extended Remote Management Control Protocol (RMCP+), i ncl uding s es sion es tabl i shment RMCP+ compl i ant authenti cati on, i ntegri ty and confi denti ality, s peci fically vi a the fol l owi ng al gorithms (all us ing IPMI i ant random number generati on): Authenti cati on: HMAC-SHA1 Integri ty: HMAC-SHA1-96 Confi denti al ity.

10 AES-CBC-128 IPMI over LAN and SoL payl oad types i n RMCP+, wi th framework for s upporti ng further payl oad types Enabl es fi rmware upgrades and IPMI trace col l ecti on vi a LAN channel Opti onal IPv4 or IPv6 parameter as s i gnment vi a di rect i nteracti on wi th DHCPv4 2 LPC/KCS implements the IPMI-defined Keyboard Controller Style interface using the Low Pin Count version of the Peripheral Component Interconnect (PCI) bus that is used for access to low speed peripherals such as management controllers. Pigeon Point BMR-A2F-VPX Reference Design Page 5 / 8 or DHCPv6 s erver or by Shel f Manager3 or other proxy Supported LAN i nterfaces wi th SmartFus i on RMII-equi pped Ethernet MAC i ncl ude: NC-SI4, tes ted wi th s el ected Intel NCs UMP (Uni vers al Management Port, a Broadcom predeces s or to NC-SI), tes ted wi th Broadcom BCM5714C Di rect Ethernet, where the LAN connecti on i s dedi cated to management traffi c, not s hared wi th the payl oad Addi ti onal s upported LAN i nterface wi th SMBus s i deband i nterface: Intel-proprietary pas s-through 3 The Pigeon Point Shelf Manager can be configured to assign IPv4 address parameters to LAN-attached IPMCs via mechanisms.