Power MOSFET - Vishay

1 IRFR120, IRFU120, SiHFR120, Siliconix S13-0171-Rev. C, 04-Feb-131 Document Number: 91266 For technical questions, contact: DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT MOSFETFEATURES Dynamic dV/dt Rating Repetitive Avalanche Rated Surface Mount (IRFR120, SiHFR120) Straight Lead (IRFU120, SiHFU120) Available in Tape and Reel Fast Switching Ease of Paralleling Material categorization: For definitions ofcompliance please see DESCRIPTIONT hird generation Power MOSFETs from Vishay provide thedesigner with the best combination of fast switching,ruggedized device design, low on-resistance DPAK is designed for surface mounting using vaporphase, infrared, or wave soldering techniques. The straightlead version (IRFU, SiHFU series) is for through-holemounting applications.

2 Power dissipation levels up to Ware possible in typical surface mount See device Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).b. VDD = 25 V, starting TJ = 25 C, L = mH, Rg = 25 , IAS = A (see fig. 12).c. ISD A, dI/dt 110 A/ s, VDD VDS, TJ 150 mm from When mounted on 1" square PCB (FR-4 or G-10 material). PRODUCT SUMMARYVDS (V)100 RDS(on) ( )VGS = 10 V (Max.) (nC)16 Qgs (nC) (nC) MOSFET GDSDPAK(TO-252)IPAK(TO-251)GDSSDGDORDERI NG INFORMATIONP ackageDPAK (TO-252)DPAK (TO-252)DPAK (TO-252)DPAK (TO-252)IPAK (TO-251)Lead (Pb)-free and Halogen-freeSiHFR120-GE3 SiHFR120TR-GE3aSiHFR120 TRR-GE3aSiHFR120 TRL-GE3aSiHFU120-GE3 Lead (Pb)-freeIRFR120 PbFIRFR120 TRPbFa IRFR120 TRRPbFa IRFR120 TRLPbFa IRFU120 PbFSiHFR120-E3 SiHFR120T-E3a SiHFR120TR-E3a SiHFR120TL-E3a SiHFU120-E3 ABSOLUTE MAXIMUM RATINGS (TC = 25 C, unless otherwise noted)

3 PARAMETER SYMBOLLIMITUNITD rain-Source Voltage VDS100V Gate-Source VoltageVGS 20 Continuous Drain CurrentVGS at 10 VTC = 25 C = 100 C Drain CurrentaIDM 31 Linear Derating C Linear Derating Factor (PCB Mount) Pulse Avalanche EnergybEAS 210mJ Repetitive Avalanche CurrentaIAR Repetitive Avalanche Maximum Power DissipationTC = 25 C PD42W Maximum Power Dissipation (PCB Mount)eTA = 25 Diode Recovery dV/dtcdV/dt Operating Junction and Storage Temperature RangeTJ, Tstg- 55 to + 150 C Soldering Recommendations (Peak Temperature)dfor 10 s260 IRFR120, IRFU120, SiHFR120, Siliconix S13-0171-Rev. C, 04-Feb-132 Document Number: 91266 For technical questions, contact: DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE.

4 THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT When mounted on 1" square PCB (FR-4 or G-10 material). Notesa. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).b. Pulse width 300 s; duty cycle 2 %.THERMAL RESISTANCE RATINGSPARAMETER Junction-to-AmbientRthJA--110 C/WMaximum Junction-to-Ambient (PCB Mount)aRthJA--50 Maximum Junction-to-Case (Drain) (TJ = 25 C, unless otherwise noted)PARAMETER SYMBOLTEST CONDITIONS Breakdown Voltage VDS VGS = 0 V, ID = 250 A 100--V VDS Temperature Coefficient VDS/TJ Reference to 25 C, ID = 1 mA C Gate-Source Threshold Voltage VGS(th)VDS = VGS, ID = 250 A Gate-Source Leakage IGSS VGS = 20 V-- 100nA Zero Gate Voltage Drain Current IDSS VDS = 100 V, VGS = 0 V --25 A VDS = 80 V, VGS = 0 V, TJ = 125 C --250 Drain-Source On-State Resistance RDS(on)

5 VGS = 10 VID = Forward Transconductance gfsVDS = 50 V, ID = DynamicInput Capacitance Ciss VGS = 0 V, VDS = 25 V,f = MHz, see fig. 5-360-pFOutput Capacitance Coss -150-Reverse Transfer Capacitance Crss -34-Total Gate Charge Qg VGS = 10 V ID = A, VDS = 80 V, see fig. 6 and 13b--16nC Gate-Source Charge Qgs ChargeQgd Delay Time td(on) VDD = 50 V, ID = A, Rg = 18 , RD = , see fig. Timetr -27-Turn-Off Delay Time td(off) -18-Fall Time tf -17-Internal Drain Inductance LD Between lead,6 mm ( ") from package and center of die contact Internal Source Body Diode CharacteristicsContinuous Source-Drain Diode Current ISMOSFET symbolshowing the integral reversep - n junction Diode Forward CurrentaISM--31 Body Diode VoltageVSDTJ = 25 C, IS = A, VGS = 0 Diode Reverse Recovery TimetrrTJ = 25 C, IF = A, dI/dt = 100 A/ sb-130260nsBody Diode Reverse Recovery CForward Turn-On TimetonIntrinsic turn-on time is negligible (turn-on is dominated by LS and LD)DSGSDGIRFR120, IRFU120, SiHFR120, Siliconix S13-0171-Rev.

6 C, 04-Feb-133 Document Number: 91266 For technical questions, contact: DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT CHARACTERISTICS (25 C, unless otherwise noted)Fig. 1 - Typical Output Characteristics, TC = 25 CFig. 2 - Typical Output Characteristics, TC = 150 CFig. 3 - Typical Transfer CharacteristicsFig. 4 - Normalized On-Resistance vs. TemperatureIRFR120, IRFU120, SiHFR120, Siliconix S13-0171-Rev. C, 04-Feb-134 Document Number: 91266 For technical questions, contact: DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT 5 - Typical Capacitance vs. Drain-to-Source VoltageFig. 6 - Typical Gate Charge vs. Gate-to-Source VoltageFig. 7 - Typical Source-Drain Diode Forward VoltageFig.

7 8 - Maximum Safe Operating AreaIRFR120, IRFU120, SiHFR120, Siliconix S13-0171-Rev. C, 04-Feb-135 Document Number: 91266 For technical questions, contact: DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT 9 - Maximum Drain Current vs. Case TemperatureFig. 10a - Switching Time Test CircuitFig. 10b - Switching Time WaveformsFig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-CasePulse width 1 sDuty factor % V+-VDSVDDVDS90 %10 %VGStd(on)trtd(off)tfIRFR120, IRFU120, SiHFR120, Siliconix S13-0171-Rev. C, 04-Feb-136 Document Number: 91266 For technical questions, contact: DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT 12a - Unclamped Inductive Test CircuitFig.

8 12b - Unclamped Inductive WaveformsFig. 12c - Maximum Avalanche Energy vs. Drain CurrentFig. 13a - Basic Gate Charge WaveformFig. 13b - Gate Charge Test +-VDD10 VVar y tp to obtainrequired F50 k 12 VCurrent regulatorCurrent sampling resistorsSame type as +-IRFR120, IRFU120, SiHFR120, Siliconix S13-0171-Rev. C, 04-Feb-137 Document Number: 91266 For technical questions, contact: DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT 14 - For N-ChannelVishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for SiliconTechnology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, andreliability data, see recoverydV/dtRipple 5 %Body diode forward dropRe-appliedvoltageReverserecoverycurr entBody diode forwardcurrentVGS = 10 Va ISDD river gate lSD VDS waveformInductor currentD = +-+++---Peak Diode Recovery dV/dt Test CircuitVDD dV/dt controlled by Rg Driver same type as ISD controlled by duty factor D - device under layout considerations Low stray inductance Ground plane Low leakage inductancecurrent transformerRgNotea.

9 VGS = 5 V for logic level devicesVDDP ackage Siliconix Revision: 16-Dec-20191 Document Number: 71197 For technical questions, contact: DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT Case OutlineVERSION 1: FACILITY CODE = YNote Dimension L3 is for reference plane height ( mm)eb3EC2 ALHP ackage Siliconix Revision: 16-Dec-20192 Document Number: 71197 For technical questions, contact: DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT 2: FACILITY CODE = NNotes Dimensioning and tolerance confirm to ASME All dimensions are in millimeters. Angles are in degrees Heat sink side flash is max. mm Radius on terminal is optionalEDL3b3Ac2 E1D1(3 )(3 )3x b2x "B"A1L2L(L1)HCSEATINGPLANECC(b)cc1b1 DETAIL "B"GAUGEPLANEL4L5 0 10 10 15 225 35 : E19-0649-Rev.

10 Q, 16-Dec-2019 DWG: 5347 Document Number: : 15-Sep-081 Package InformationVishay Siliconix TO-251AA (HIGH VOLTAGE)Notes1. Dimensioning and tolerancing per ASME Dimension are shown in inches and Dimension D and E do not include mold flash. Mold flash shall not exceed mm ( ") per side. These dimensions are measured at theoutermost extremes of the plastic Thermal pad contour optional with dimensions b4, L2, E1 and Lead dimension uncontrolled in Dimension b1, b3 and c1 apply to base metal Outline conforms to JEDEC outline , b3(b, b2)c1(c)Section B - B and C - CDAc2cLead tip55(Datum A)Thermal PADE14D1 View A - AA1 AACS eatingplaneCCBB 1 2B44435L1LL33 x b23 x b3b4E2 x 10'15'0'15' 225'35'25'35' : S-82111-Rev. A, 15-Sep-08 DWG: 5968 Application Note 826 Vishay Siliconix Document Number: : 21-Jan-083 APPLICATION NOTERECOMMENDED MINIMUM PADS FOR DPAK (TO-252) ( )Recommended Minimum PadsDimensions in Inches/(mm) ( ) ( ) ( ) ( ) ( ) ( )Return to IndexReturn to IndexLegal Disclaimer Revision: 01-Jan-20191 Document Number: 91000 Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.