Programmable Serial Channel 8-bit Microcontroller

1 1 Features Compatible with MCS-51 Products 8K Bytes of In-System reprogrammable flash memory Endurance: 1,000 Write/Erase Cycles Fully Static Operation: 0 Hz to 24 MHz Three-level Program memory Lock 256 x 8-bit Internal RAM 32 Programmable I/O Lines Three 16-bit Timer/Counters Eight Interrupt Sources Programmable Serial Channel Low-power Idle and Power-down ModesDescriptionThe AT89C52 is a low-power, high-performance CMOS 8-bit microcomputer with 8 Kbytes of flash Programmable and erasable read only memory (PEROM). The deviceis manufactured using Atmel s high-density nonvolatile memory technology and iscompatible with the industry-standard 80C51 and 80C52 instruction set and on-chip flash allows the program memory to be reprogrammed in-system or by aconventional nonvolatile memory programmer. By combining a versatile 8-bit CPUwith flash on a monolithic chip, the Atmel AT89C52 is a powerful microcomputerwhich provides a highly-flexible and cost-effective solution to many embedded Microcontroller with 8K Bytes FlashAT 8 9 C 5 2 Not Recommended for New Designs.

2 Use 0313H 02/00 Pin (RXD) (TXD) (INT0) (INT1) (T0) ) (AD4) (AD5) (AD6) (AD7)EA/ (A15) (A14) (A13)44434241403938373635341213141516171 819202122(WR) (RD) (A8) (A9) (A10) (A11) (A12) (T2 EX) (T2) (AD0) (AD1) (AD2) (AD3)PDIP1234567891011121314151617181920 4039383736353433323130292827262524232221 (T2) (T2 EX) (RXD) (TXD) (INT0) (INT1) (T0) (T1) (WR) (RD) (AD0) (AD1) (AD2) (AD3) (AD4) (AD5) (AD6) (AD7)EA/ (A15) (A14) (A13) (A12) (A11) (A10) (A9) (A8) (RXD) (TXD) (INT0) (INT1) (T0) (T1) (AD4) (AD5) (AD6) (AD7)EA/ (A15) (A14) (A13)65432144434241401819202122232425262 728(WR) (RD) 2 XTAL1 GNDNC(A8) (A9) (A10) (A11) (A12) (T2 EX) (T2) (AD0) (AD1) (AD2) (AD3)AT89C522 Block DiagramPORT 2 DRIVERSPORT - 0 LATCHRAMPROGRAMADDRESSREGISTERBUFFERPCIN CREMENTERPROGRAMCOUNTERDPTRRAM , Serial PORT,AND TIMER BLOCKSSTACKPOINTERACCTMP2 TMP1 ALUPSWTIMINGANDCONTROLPORT 3 LATCHPORT 3 - 1 LATCHPORT 1 - / VPPRSTPORT 0 - AT89C52 provides the following standard features: 8 Kbytes of flash , 256 bytes of RAM, 32 I/O lines, three 16-bittimer/counters, a six-vector two-level interrupt architecture,a full-duplex Serial port, on-chip oscillator, and clock cir-cuitry.

3 In addition, the AT89C52 is designed with static logicfor operation down to zero frequency and supports twosoftware selectable power saving modes. The Idle Modestops the CPU while allowing the RAM, timer/counters, Serial port, and interrupt system to continue Power-down mode saves the RAM contents butfreezes the oscillator, disabling all other chip functions untilthe next hardware DescriptionVCCS upply 0 Port 0 is an 8-bit open drain bi-directional I/O port. As anoutput port, each pin can sink eight TTL inputs. When 1sare written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external pro-gram and data memory . In this mode, P0 has 0 also receives the code bytes during flash program-ming and outputs the code bytes during programverification. External pullups are required during programverification.

4 Port 1 Port 1 is an 8-bit bi-directional I/O port with internal Port 1 output buffers can sink/source four TTL 1s are written to Port 1 pins, they are pulled high bythe internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will sourcecurrent (IIL) because of the internal pullups. In addition, and can be configured to be thetimer/counter 2 external count input ( ) and thetimer/counter 2 trigger input ( ), respectively, asshown in the following 1 also receives the low-order address bytes duringFlash programming and 2 Port 2 is an 8-bit bi-directional I/O port with internal Port 2 output buffers can sink/source four TTL 1s are written to Port 2 pins, they are pulled high bythe internal pullups and can be used as inputs. As inputs,Port 2 pins that are externally being pulled low will sourcecurrent (IIL) because of the internal pullups.

5 Port 2 emits the high-order address byte during fetchesfrom external program memory and during accesses toexternal data memory that use 16-bit addresses (MOVX In this application, Port 2 uses strong internal pul-lups when emitting 1s. During accesses to external datamemory that use 8-bit addresses (MOVX @ RI), Port 2emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and somecontrol signals during flash programming and 3 Port 3 is an 8-bit bi-directional I/O port with internal Port 3 output buffers can sink/source four TTL 1s are written to Port 3 pins, they are pulled high bythe internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will sourcecurrent (IIL) because of the 3 also serves the functions of various special featuresof the AT89C51, as shown in the following 3 also receives some control signals for flash pro-gramming and input.)

6 A high on this pin for two machine cycles whilethe oscillator is running resets the device. ALE/PROGA ddress Latch Enable is an output pulse for latching thelow byte of the address during accesses to external mem-ory. This pin is also the program pulse input (PROG) duringFlash programming. In normal operation, ALE is emitted at a constant rate of 1/6the oscillator frequency and may be used for externalPort PinAlternate (external count input to Timer/Counter 2), (Timer/Counter 2 capture/reload trigger anddirection control)Port PinAlternate ( Serial input port) ( Serial output port) (external interrupt 0) (external interrupt 1) (timer 0 external input) (timer 1 external input) (external data memory write strobe) (external data memory read strobe)AT89C524timing or clocking purposes. Note, however, that one ALEpulse is skipped during each access to external datamemory.

7 If desired, ALE operation can be disabled by setting bit 0 ofSFR location 8EH. With the bit set, ALE is active only dur-ing a MOVX or MOVC instruction. Otherwise, the pin isweakly pulled high. Setting the ALE-disable bit has noeffect if the Microcontroller is in external execution Store Enable is the read strobe to external pro-gram memory . When the AT89C52 is executing code from external pro-gram memory , PSEN is activated twice each machinecycle, except that two PSEN activations are skipped duringeach access to external data memory . EA/VPPE xternal Access Enable. EA must be strapped to GND inorder to enable the device to fetch code from external pro-gram memory locations starting at 0000H up to , however, that if lock bit 1 is programmed, EA will beinternally latched on reset. EA should be strapped to VCC for internal pin also receives the 12-volt programming enable volt-age (VPP) during flash programming when 12-voltprogramming is to the inverting oscillator amplifier and input to theinternal clock operating from the inverting oscillator 1.

8 AT89C52 SFR Map and Reset Values0F8H0 FFH0F0HB000000000F7H0E8H0 EFH0E0 HACC000000000E7H0D8H0 DFH0D0 HPSW000000000D7H0C8HT2 CON00000000T2 MODXXXXXX00 RCAP2L00000000 RCAP2H00000000TL200000000TH2000000000 CFH0C0H0C7H0B8 HIPXX0000000 BFH0B0HP3111111110B7H0A8 HIE0X0000000 AFH0A0HP2111111110A7H98 HSCON00000000 SBUFXXXXXXXX9FH90HP11111111197H88 HTCON00000000 TMOD00000000TL000000000TL100000000TH0000 00000TH1000000008FH80HP011111111SP000001 11 DPL00000000 DPH00000000 PCON0 XXX000087 HAT89C525 Special Function RegistersA map of the on-chip memory area called the Special Func-tion Register (SFR) space is shown in Table that not all of the addresses are occupied, and unoc-cupied addresses may not be implemented on the accesses to these addresses will in general returnrandom data, and write accesses will have an indetermi-nate software should not write 1s to these unlisted loca-tions, since they may be used in future products to invokenew features.

9 In that case, the reset or inactive values ofthe new bits will always be 2 Registers Control and status bits are contained inregisters T2 CON (shown in Table 2) and T2 MOD (shown inTable 4) for Timer 2. The register pair (RCAP2H, RCAP2L)are the Capture/Reload registers for Timer 2 in 16-bit cap-ture mode or 16-bit auto-reload Registers The individual interrupt enable bits arein the IE register. Two priorities can be set for each of thesix interrupt sources in the IP MemoryThe AT89C52 implements 256 bytes of on-chip RAM. Theupper 128 bytes occupy a parallel address space to theSpecial Function Registers. That means the upper 128bytes have the same addresses as the SFR space but arephysically separate from SFR an instruction accesses an internal location aboveaddress 7FH, the address mode used in the instructionspecifies whether the CPU accesses the upper 128 bytesof RAM or the SFR space.

10 Instructions that use directaddressing access SFR space. For example, the following direct addressing instructionaccesses the SFR at location 0A0H (which is P2). MOV 0A0H, #dataTable 2. T2 CON Timer/Counter 2 Control RegisteT2 CON Address = 0C8 HReset Value = 0000 0000 BBit AddressableBitTF2 EXF2 RCLKTCLKEXEN2TR2C/T2CP/RL276543210 Symbol FunctionTF2 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK = 1 or TCLK = 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).RCLKR eceive clock enable. When set, causes the Serial port to use Timer 2 overflow pulses for its receive clock in Serial port Modes 1 and 3.