Quartus® Prime はじめてガイド

1 ALTIMA Company, MACNICA, Inc. ELSENA,Inc. quartus Prime Signal Tap 1 quartus Prime Signal Tap / Rev. 1 2018 1 2/28 ALTIMA Company, MACNICA, Inc. / ELSENA,Inc..3 ..4 .. 4 .. 4 .. 4 ..5 FPGA .. 5 .. 5 .. 6 .. 6 ..7 Signal Tap .. 7 4 1 1. STP .. 7 4 1 2. STP .. 9 Signal Tap .. 10 4 2 1.. 10 4 2 2.. 11 4 2 3.. 13 4 2 4.

2 RAM .. 13 4 2 5.. 14 .. 19 4 3 1.. 19 4 3 2.. 22 4 3 3.. 22 .. 23 FPGA .. 24 Signal Tap .. 24 .. 25 4 7 1.. 25 4 7 2.. 26 4 7 3.. 27 ..28 quartus Prime Signal Tap / Rev. 1 2018 1 3/28 ALTIMA Company, MACNICA, Inc. / ELSENA,Inc. quartus Prime quartus Prime quartus Prime FPGA FPGA I/O FPGA I/O Signal Tap Signal Tap Signal Tap quartus Prime FPGA Signal Tap IP

3 JTAG quartus Prime quartus Prime Signal Tap / Rev. 1 2018 1 4/28 ALTIMA Company, MACNICA, Inc. / ELSENA,Inc. Signal Tap 1 JTAG FPGA Design Debugging with the Signal Tap Logic Analyzer ( quartus Prime Standard Edition) Design Debugging with the Signal Tap Logic Analyzer ( quartus Prime Pro Edition)

4 Signal Tap quartus Prime SignalTap II Signal Tap quartus Prime Lite Edition quartus Prime Standard Edition quartus Prime Pro Edition quartus Prime Lite Edition TalkBack TIPS quartus Prime Programmer and Tools FPGA II USB Blaster II FPGA USB Blaster FPGA EthernetBlaster II Stratix Arria Cyclone MAX 10 quartus Prime Signal Tap / Rev.

5 1 2018 1 5/28 ALTIMA Company, MACNICA, Inc. / ELSENA,Inc. CPLD MAX V Signal Tap 10 pin FPGA JTAG FPGA Signal Tap FPGA Signal Tap quartus Prime Signal Tap (*.stp) Signal Tap Instance Manager STP 10% (post fitting) Signal Tap JTAG (TCK TDI TDO TMS) ALTGXB IP LVDS / (SERDES)

6 DDR / DDR2 DQ DQS Can t fit no fit quartus Prime Signal Tap / Rev. 1 2018 1 6/28 ALTIMA Company, MACNICA, Inc. / ELSENA,Inc. Signal Tap Signal Tap Analysis and Elaboration Analysis and Elaboration Processing Start Start Analysis and Elaboration Signal Tap Signal Tap Signal Tap FPGA Signal Tap

7 quartus Prime Signal Tap / Rev. 1 2018 1 7/28 ALTIMA Company, MACNICA, Inc. / ELSENA,Inc. Signal Tap Signal Tap IP 2 - Signal Tap (*.stp) - IP Catalog Altera SignalTap II Logic Analyzer Signal Tap ( STP ) 4 1 1. STP File New Verification/Debugging Files Signal Tap Logic Analyzer File STP Tools Signal Tap Logic Analyzer STP STP STP quartus Prime Signal Tap / Rev.

8 1 2018 1 8/28 ALTIMA Company, MACNICA, Inc. / ELSENA,Inc. 6 STP Instance Manager auto_signaltap_0 Signal Tap IP Rename Instance Signal Tap IP 1 FPGA Signal Tap IP Instance Manager Create Instance Signal Tap IP

9 Hierarchy Display Instance Manager Node List JTAG Chain Configuration Signal Configuration Hierarchy Display Data Log Enabled quartus Prime Signal Tap / Rev. 1 2018 1 9/28 ALTIMA Company, MACNICA, Inc. / ELSENA,Inc. 4 1 2. STP Signal Tap IP STP Signal Tap IP STP quartus Prime Signal Tap IP STP File Save Add file to current project (S) Do you want to enable Signal Tap File < >.

10 Stp for the current project? Yes STP Signal Tap Logic Analyzer Assignments Settings STP STP Input Data and Trigger is empty quartus Prime Signal Tap / Rev. 1 2018 1 10/28 ALTIMA Company, MACNICA, Inc. / ELSENA,Inc. Signal Tap STP Signal Tap IP 4 2 1.