Raphael Reference Manual - www-eng.lbl.gov

1 RaphaelTMInterconnect Analysis ProgramReference ManualVersion , March 2006iiCopyright Notice and Proprietary InformationCopyright 2006 Synopsys, Inc. All rights reserved. This software and documentation contain confidential and proprietary information that is the property of Synopsys, Inc. The software and documentation are furnished under a license agreement and may be used or copied only in accordance with the terms of the license agreement. No part of the software and documentation may be reproduced, transmitted, or translated, in any form or by any means, electronic, mechanical, Manual , optical, or otherwise, without prior written permission of Synopsys, Inc., or as expressly provided by the license to Copy DocumentationThe license agreement with Synopsys permits licensee to make copies of the documentation for its internal use only.

2 Each copy shall include all copyrights, trademarks, service marks, and proprietary rights notices, if any. Licensee must assign sequential numbers to all copies. These copies shall contain the following legend on the cover page: This document is duplicated with the permission of Synopsys, Inc., for the exclusive use of _____ and its employees. This is copy number _____. Destination Control StatementAll technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader s responsibility to determine the applicable regulations and to comply with , INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR Trademarks ( )Synopsys, AMPS, Arcadia, C Level Design, C2 HDL, C2V, C2 VHDL, Cadabra, Calaveras Algorithm, CATS, CRITIC, CSim, Design Compiler, DesignPower, DesignWare, EPIC, Formality, HSIM, HSPICE, Hypermodel, iN-Phase, in-Sync, Leda, MAST, Meta, Meta-Software, ModelTools, NanoSim, OpenVera, PathMill, Photolynx, Physical Compiler, PowerMill, PrimeTime, RailMill, RapidScript, Saber, SiVL, SNUG, SolvNet, Superlog, System Compiler, TetraMAX, TimeMill, TMA, VCS, Vera, and Virtual Stepper are registered trademarks of Synopsys, ( )

3 Active Parasitics, AFGen, Apollo, Apollo II, Apollo-DPII, Apollo-GA, ApolloGAII, Astro, Astro-Rail, Astro-Xtalk, Aurora, AvanTestchip, AvanWaves, BCView, Behavioral Compiler, BOA, BRT, Cedar, ChipPlanner, Circuit Analysis, Columbia, Columbia-CE, Comet 3D, Cosmos, CosmosEnterprise, CosmosLE, CosmosScope, CosmosSE, Cyclelink, Davinci, DC Expert, DC Professional, DC Ultra, DC Ultra Plus, Design Advisor, Design Analyzer, Design Vision, DesignerHDL, DesignTime, DFM-Workbench, Direct RTL, Direct Silicon Access, Discovery, DW8051, DWPCI, Dynamic-Macromodeling, Dynamic Model Switcher, ECL Compiler, ECO Compiler, EDAnavigator, Encore, Encore PQ, Evaccess, ExpressModel, Floorplan Manager, Formal Model Checker, FoundryModel, FPGA Compiler II, FPGA Express, Frame Compiler, Galaxy, Gatran, HANEX, HDL Advisor, HDL Compiler, Hercules, Hercules-Explorer, Hercules-II, Hierarchical Optimization Technology, High Performance Option, HotPlace, HSIM plus, HSPICE-Link, iN-Tandem, Integrator, Interactive Waveform Viewer, i-Virtual Stepper, Jupiter, Jupiter-DP, JupiterXT, JupiterXT-ASIC, JVXtreme, Liberty, Libra-Passport, Library Compiler, Libra-Visa, Magellan, Mars, Mars-Rail, Mars-Xtalk, Medici, Metacapture, Metacircuit, Metamanager, Metamixsim, Milkyway, ModelSource, Module Compiler, MS-3200, MS-3400, Nova Product Family, Nova-ExploreRTL, Nova-Trans, Nova-VeriLint, Nova-VHDL lint, Optimum Silicon, Orion_ec, Parasitic View, Passport, Planet, Planet-PL, Planet-RTL, Polaris, Polaris-CBS, Polaris-MT, Power Compiler, PowerCODE, PowerGate, ProFPGA, ProGen, Prospector, Protocol Compiler, PSMGen, Raphael , Raphael -NES, RoadRunner, RTL Analyzer, Saturn, ScanBand.

4 Schematic Compiler, Scirocco, Scirocco-i, Shadow Debugger, Silicon Blueprint, Silicon Early Access, SinglePass-SoC, Smart Extraction, SmartLicense, SmartModel Library, Softwire, Source-Level Design, Star, Star-DC, Star-MS, Star-MTB, Star-Power, Star-Rail, Star-RC, Star-RCXT, Star-Sim, Star-SimXT, Star-Time, Star-XP, SWIFT, Taurus, TimeSlice, TimeTracker, Timing Annotator, TopoPlace, TopoRoute, Trace-On-Demand, True-Hspice, TSUPREM-4, TymeWare, VCS Express, VCSi, Venus, Verification Portal, VFormal, VHDL Compiler, VHDL System Simulator, VirSim, and VMC are trademarks of Synopsys, Marks (SM)MAP-in, SVP Caf , and TAP-in are service marks of Synopsys, is a trademark of the Open SystemC Initiative and is used under and AMBA are registered trademarks of ARM other product or company names may be trademarks of their respective owners.

5 Draft 5/26/06 Table of ContentsCONTENTSRA This Manual xiAudience .. xiRelated Publications .. xiConventions .. xiiCustomer Support .. xiiiAccessing SolvNet .. xiiiContacting the Synopsys Technical Support Center .. xiiiChapter 1 Using Raphael1-1 Overview.. 1-12D and 3D Solvers .. 1-1 GDS II Stream Format Interface .. 1-3 Raphael Graphical User Interface .. 1-3 Field Solvers .. 1-3RC2 .. 1-3RC2-BEM .. 1-4RC3 .. 1-4RC3-BEM .. 1-4RI3 .. 1-4 RIL .. 1-4 GDS II Interface .. 1-5 DPLOT .. 1-5 Taurus Visual Support .. 1-6 Command Description Format .. 1-6 Command Editor.. 1-7 Naming Convention for Examples .. 1-7 Raphael Flow to Extract Parasitics .. 1-8 Flow Diagram .. 1-9 Draft 5/26/06 Table of ContentsRaphael Tutorialiv RA 2 RC2: 2D Resistance, Capacitance, and Inductance2-1 Introduction.

6 2-1RC2 Input File .. 2-3 PARAM .. 2-4 BOX .. 2-5 CIRC1 .. 2-6 CIRC2 .. 2-8 POLY .. 2-10 COPY .. 2-11 WINDOW .. 2-12 MERGE .. 2-13 POTENTIAL .. 2-14 CAPACITANCE .. 2-14 CURRENT .. 2-15 RESISTANCE .. 2-15 INDUCTANCE .. 2-16Z0 .. 2-16 SPICE.. 2-16 EXTRACT .. 2-18 OPTIONS.. 2-19 Theory of Floating Conductors .. 2-20 Selection of Linear Solver .. 2-21 Examples Using RC2 .. 2-22 Example 1: Inductance Simulation of a Line Above Ground Plane .. 2-22 Example 2: Three Lines Above a Plane .. 2-24 Example 3: Current Density and Resistance Analysis.. 2-29 Example 4: SPICE Model Extraction .. 2-32 Example 5: Floating Conductors .. 2-34 Example 6: Anisotropic Dielectric Materials.. 2-36 References.. 2-38 Chapter 3 RC2-BEM: 2D Field Solver by Boundary Element Method3-1 Introduction.. 3-1 Theoretical Background.

7 3-2 Green s Function .. 3-2FD, FEM, BEM Differences .. 3-2RC2-BEM Command Line Options .. 3-3 Notes on the Current Version of RC2-BEM.. 3-4 Comparison of RC2-BEM and RC2 .. 3-5 Example 1: Microstrip Lines Above a Ground Plane .. 3-6 Example 2: Inhomogeneous Dielectric Layers .. 3-9 Draft 5/26/06 Raphael TutorialTable of ContentsRA 3: Modeling of the Power-Plane Resistance .. 3-13 References.. 3-15 Chapter 4 RC3: 3D Resistance, Capacitance, and Thermal Resistance4-1 Introduction.. 4-1RC3 Input File .. 4-3 PARAM .. 4-4 BLOCK .. 4-5 CYLINDER .. 4-9 SPHERE.. 4-11 POLY3D .. 4-12 COPY3D .. 4-15 MERGE .. 4-16 WINDOW3D .. 4-17 POTENTIAL .. 4-19 CAPACITANCE .. 4-19 CURRENT .. 4-19 RESISTANCE .. 4-19 TEMPERATURE.. 4-19 THERMORES .. 4-20 EXTRACT .. 4-20 OPTIONS.. 4-20 Theory of Floating Conductors.

8 4-21 Selecting Linear Solver.. 4-21 Creating Graphics Files .. 4-22 Interface to Taurus Device .. 4-23 Examples.. 4-24 Example 1: Current Density and Resistance of a Cylindrical Via .. 4-25 Example 2: Capacitance and Potential Analysis of a Cross-Over Structure .. 4-29 Example 3: Floating-Gate Transistor .. 4-35 Example 4: Anisotropic Dielectric Materials.. 4-37 Chapter 5 RC3-BEM: 3D Field Solver by Boundary Element Method5-1 Introduction.. 5-1RC3-BEM Command-Line Options .. 5-2 Notes on the Current Version of RC3-BEM.. 5-3 Comparison of RC3-BEM and RC3 .. 5-4 Example 1: Single Plate Above a Plane.. 5-4 Example 2: Crossover Capacitance .. 5-8 Example 3: A Trapezoidal Conductor Between Two Draft 5/26/06 Table of ContentsRaphael Tutorialvi RA Planes.

9 5-10 Example 4: Substrate Resistance .. 5-12 Chapter 6 RI3: 3D Resistance and Inductance with Skin Effect6-1 Introduction.. 6-1 Theory .. 6-1 Program RI3 .. 6-4RI3 Input File .. 6-5 PARAM .. 6-6 NODE.. 6-6 PLANE_NODE .. 6-7 SINGLE_BAR .. 6-9 MULTI_BAR.. 6-10 PLANE.. 6-12 OPTIONS3I .. 6-13 MATRIX .. 6-13 MERGE3I .. 6-14 EXT .. 6-14 REF .. 6-15 FREQUENCY .. 6-15 ADMITTANCE .. 6-15 SPARAMETER .. 6-16 OUTPUT .. 6-16 Equivalent Circuit .. 6-16 Selection of Extraction Algorithm .. 6-17 Examples.. 6-17 Example 1(raexi31): Inductance of Two Parallel Microstrips.. 6-17 Example 2 (raexi32): Skin Effect Simulation .. 6-20 Example 3 (raexi33): Circular Ring Above Ground Plane .. 6-23 Example 4 (raexi34): Inductance of Four Bond Wires .. 6-27 References.. 6-31 Chapter 7 Raphael Interconnect Library7-1 Introduction.

10 7-1 Raphael Interconnect Library .. 7-1 Running RIL .. 7-3 RIL Interactive Commands.. 7-5 ADD .. 7-5 CHECK .. 7-5 GENERATE.. 7-5 INPUT CHECK / PLOTS .. 7-6 LIST .. 7-6 PRINT .. 7-6 Draft 5/26/06 Raphael TutorialTable of ContentsRA .. 7-6 SAVE .. 7-7 VISUALIZE.. 7-7 TABLE.. 7-7 QUIT .. 7-7 Directory Structure and Files .. 7-8 Customization .. 7-8start_up File .. 7-8 RIL Environment Variables .. 7-9 SPICE Netlist Generation and Naming Convention .. 7-10 RIL Example Sessions .. 7-12 Session 1: 3D Example .. 7-12 Session 2: 2D Example .. 7-16 Session 3: RIL and STUDIO Visualize .. 7-21 Chapter 8 Advanced Parser of Interconnect Structures8-1 Overview.. 8-1 Running APIS .. 8-3 Using the APIS Program.. 8-5 APIS Input and Output Files .. 8-5 Assigning Metal and Text Layers .. 8-6 Boolean and Size Operations at Layout Layers.