SP7651 Wide Input Voltage Range 3A,900kHz, Buck Regulator

1 Rev J: 3/ 4/07 SP765 wide Input Voltage Range 3A, 900khz , buck Regulator Copyright 2007 Sipex CorporationFEATURES to 20V Step Down Achieved Using Dual Input Output Voltage down to 3A Output Capability (Up to 5A with Air Flow) Built in Low RDSON Power FETs (40 m typ) Highly Integrated Design, Minimal Components 900 kHz Fixed Frequency Operation UVLO Detects Both VCC and VIN Over Temperature Protection Short Circuit Protection with Auto-Restart wide BW Amp Allows Type II or III Compensation Programmable Soft Start Fast Transient Response High Efficiency: Greater than 92% Possible Asynchronous Start-Up into a Pre-Charged Output Small 7mm x 4mm DFN Package Patent #6,922,04 The SP7651 is a high Voltage synchronous step-down switching Regulator optimized for high efficiency.

2 The part is designed to be especially attractive for dual supply, 2V step down with 5V used to power the controller. This lower VCC Voltage minimizes power dissipation in the part. The SP765 is designed to provide a fully integrated buck Regulator solution using a fixed 900khz frequency, PWM Voltage mode architecture. Protection features include UVLO, thermal shutdown and output short circuit protection. The SP765 is available in the space saving 7mm X 4mm DFN APPLICATION CIRCUITDESCRIPTION CBST6800pFL , Irate= SP7651 PGND PGND2 PGND3 GND4 VFB5 COMP6 UVIN7 GND8SS9 VIN 0 VIN VIN 2 VIN 3LX 4LX 5LX 6NC 7 BST 8 GND 9 GND20 GND2 VCC22LX23LX24LX25LX26 DBSTCSS 5nFCP.

3 5k , %GNDC322uFNotes:12 VVIN1. U1 Bottom-Side Layout shouldhave three contacts isolated fromone another: Vin, SWNODE, and 5k ,1%Cz3 50pFCz2 ,000pFR 68. k , %Rz2 5k,1%CF 00pFfs=900 Khz+5V VCC ENABLE2. RSET= ( ) (KOhm) (note 2)16 VSolvedbyTMSP7651 wide Input Voltage Range 3 Amp 900khz buck RegulatorSP7651 DFN PACKAGE7mm x 4mmBOTTOM VIEWH eatsink Pad 1 Connect to LxHeatsink Pad 2 Connect to GNDH eatsink Pad 3 Connect to VIN1234567891011121314151617181920212223 242526 PGNDPGNDPGNDGNDVFBCOMPUVINGNDSSVINVINVIN VINLXLXLXLXVCCGNDGNDGNDBSTNCLXLXLXPin 27 Pin 28 Pin 29 SolvedbyTM2 Rev J: 3/ 4/07 SP765 wide Input Voltage Range 3A, 900khz , buck Regulator Copyright 2007 Sipex CorporationUnless otherwise specified.

4 -40 C < TAMB < 85 C, -40 C< Tj <125 C, < VCC < , 3V< Vin < 20V, BST=LX + 5V, LX = GND = , UVIN = , CVCC = F, CCOMP = 0. F, CSS = 50nF, Typical measured at VCC = 5V. The denotes the specifications which apply over the full temperature Range , unless otherwise specified. VCC ..7 VVIN ..22 VILX ..5 ABST ..35 VLX-BST .. to 7 VLX ..- V to 20 VAll other pins .. to VCC+ Temperature ..-65 C to 150 CPower Dissipation ..Internally LimitedESD Rating ..2kV HBMT hermal Resistance JC .. 5 C/W ABSOLUTE MAXIMUM RATINGSELECTRICAL CHARACTERISTICST hese are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied.

5 Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. CURRENTVcc Supply Current (No switching) .53mAVfb = Vcc Supply Current (switching)8 2mA BST Supply Current (No switching) = BST Supply Current (switching)46mA PROTECTION: UVLOVcc UVLO Start UVLO Hysteresis 00200300mVUVIN Start UVIN Hysteresis200300400mVUVIN Input Current AUVIN= AMPLIFIER REFERENCEE rror Amplifier Gain Config., Measure Vfb; Vcc =5 V, T=25 CError Amplifier ReferenceOver Line and 2V Error Amplifier Transconductance6mA/VError Amplifier Gain60dBNo LoadCOMP Sink Current 50 AVfb = , COMP= Source Current 50 AVfb = , COMP= Input Bias Current50200nAVfb = Internal Pole4 MHzCOMP = , TA=25 CCOMP Clamp Temp.

6 Coefficient-2mV/ C3 Rev J: 3/ 4/07 SP765 wide Input Voltage Range 3A, 900khz , buck Regulator Copyright 2007 Sipex CorporationELECTRICAL CHARACTERISTICSU nless otherwise specified: -40 C < TAMB < 85 C, -40 C<Tj<125 C, < VCC < , 3V<Vin<20V, BST=LX + 5V, LX = GND = , UVIN = , CVCC = F, CCOMP = 0. F, CSS = 50nF, Typical measured at VCC = 5V. The denotes the specifications which apply over the full temperature Range , unless otherwise specified. LOOP: PWM COMPARATOR, RAMP & LOOP DELAY PATHRamp ..28 VRAMP Offset.

7 VTA = 25 C, RAMP COMP until GH starts SwitchingRAMP Offset Temp. Coefficient-2mV/ CGH Minimum Pulse Width90 80ns Maximum Controllable Duty Ratio9297%Maximum Duty Ratio Measured just before pulsing beginsMaximum Duty Ratio 00%Valid for 20 cyclesInternal Oscillator Ratio8 0900990kHz TIMERS: SOFTSTARTSS Charge Current: 0 ASS Discharge Current: mA Fault Present, SS = : Short Circuit & ThermalShort Circuit Threshold Measured Vref ( ) - VFBH iccup Timeout 200msVfb = of Allowable Clock Cycles at 100% Duty Cycle20 CyclesMinimum GL Pulse After 20 = Shutdown Temperature 45 CVfb = Recovery Temperature 35 CThermal Hysteresis 0 COUTPUT: POWER STAGEHigh Side Rdson40m Vcc = 5V ; Iout = 3A Tamb = 25 CSynchronous FET Rdson 40m Vcc = 5V.

8 Iout = 3A Tamb = 25 CMaximum Output Current3A4 Rev J: 3/ 4/07 SP765 wide Input Voltage Range 3A, 900khz , buck Regulator Copyright 2007 Sipex CorporationGeneral OverviewThe SP7651 is a fixed frequency, Voltage mode, synchronous PWM Regulator opti-mized for high efficiency. The part has been designed to be especially attractive for split plane applications utilizing 5V to power the controller and to 20V for step down heart of the SP765 is a wide bandwidth transconductance amplifier designed to ac-commodate Type II and Type III compensa-tion schemes.

9 A precision reference, present on the positive terminal of the error amplifier, permits the programming of the output Voltage down to via the VFB pin. The output of the error amplifier, COMP, which is compared to a . V peak-to-peak ramp, is responsible for trailing edge PWM control. This Voltage ramp, and PWM control logic are governed by the internal oscillator THEORY OF OPERATION that accurately sets the PWM frequency to SP765 contains two unique control features that are very powerful in distributed applications. First, asynchronous driver con-trol is enabled during startup, to prohibit the low side NFET from pulling down the output until the high side NFET has attempted to turn on.

10 Second, a 100% duty cycle timeout ensures that the low side NFET is periodically enhanced during extended periods at 100% duty cycle. This guarantees the synchronized refreshing of the BST capacitor during very large duty SP765 also contains a number of valuable protection features. Programmable UVLO allows the user to set the exact VIN value at which the conversion Voltage can PIN DESCRIPTIONPin #Pin NameDescription -3 PgndGround connection for the synchronous rectifier4,8, 9-2 GNDG round Pin. The control circuitry of the IC and lower power driver are refer-enced to this pin.