電子デバイス工学 - Tatsuru Shirafuji

1 (2) MOS FET (2-2) MOS ( ) (2-3) MOS MIS q Mq Sq MIS M= S vs. MIS M S VFB VG=0 VG=VFB FBTITVVV+= S MIS MIS (Fixed charge) (Mobile ionic charge) (Oxide trapped charge) SiO2 SiO2 X SiO2 Na K S. M. Sze and Kwok K. Ng: Physics of Semiconductor Devices 3rd Ed.

2 (Wiley Interscience, 2007, New Jersey) MOScapacitanceGatevoltage0 PositiveNegative VTIdeal MOS VT OXIFCIFCCQV = CV VG QIFC NOFC(z) = OX0 OXOFCOXOFCd)(CdzdzzNqVIFC: Interface Fixed Charge OFC: Oxide Fixed Charge MOScapacitanceGatevoltage0 PositiveNegative VTIdeal MOSVT MOSFET VT MOS OXFA0 SFTIT222 CqNVV +==OX0 OXOXyC =FiFEEq = MOS VT VT OFCIFCFBTITVVVVV + ++=VFB VIFC VOFC (Interface-trapped charge)

3 Si EF CV VG EF MOScapacitanceGatevoltage0 PositiveNegativeIdeal MOSP ositive chargeat interfaceNegativecharge atinterfaceEF= EiE. H. Nicollian and J. R. Brews: MOS (Metal Oxide Semiconductor) Physics and Technology (1982, Wiley, New Work) Impurity InterstitialVacancySelf InterstitialSubstitutional MOS Marius Grundmann: The Physics of Semiconductors - An Introduction Including Nanophysics and Applications 2nd Ed.

4 (Springer, Berlin, 2010) MOSFET VG>VTVD=smallIDn+n+Lp-Sichanneldepletion layerVG>VTVD=VDSatIDn+n+p-Sipinch-offpoi ntVG>VTVD>VDSatIDn+n+p-Sipinch-offpointL MOSFET JFET EFEiECEVq FqV(x)q Fq S(x)DepletionLayerInversionLayeryy1y2n+n +zxydxW0L VD x Ex VG y Ey x x V(x) )(2)(FSxVx+= )(GOXxVVV = QS )(TOXOXSVVCQ = VT yy1y2 QQIQDqNAQM-yoxQS= QI+QD~ QIQM= -QSQI>>QDMOSFET ISQQ QI>>QD xEWQI ID=dxxdVdxdEx)(S = = x Ex {}dxxdVxVVVWCI)()(TGOXD = n+n+zxydxW0 Lyy1y2 QQIQDqNAQM-yoxQS= QI+QD~ QIQM= -QSQI>>QDMOSFET {}{}()() = = = 2 DDTGOX02 TGOX0 TGOX0 TGOX21)(21)()(d)(dd)(d)(DDVVVVWCxVxVVVWC xVxVVVWCxxxVxVVVWCVVL n+n+zxydxW0LD0 DdLIxIL= ()[]2 DDTGOXD221 VVVVWCLI = VP ID/ VD=0 PTGDSatVVVV =()

5 []01 DTGOXDD= = VVVWCLVI VDSat ()2 POX2 TGOXDSat22 VCLWVVCLWI = =MOSFET IV 543210( ID/ (WCOX /2L) )1/2543210 Gate volt age (VG- VT) (V)1086420 Normalized drain current ID / (WCOX /2L)543210 Gate volt age (VG- VT) (V) ID vs. VG ()[]2 DDTGOXD221 VVVVWCLI = ()2 TGOXDSat2 VVCLWI = ()DTGOXDVVVLWCI = VD VD<<VG-VT DOXGDmVLWCVIg = =VD VG-VT<<VD ()TGOXGDSatmVVLWCVIg = = FET ID ID1/2 VG-VT n-channelNormallyOFFE nhancementNormallyONDepletionp-channelSG Dn+pn+SGDpn-channeln+n+SGDp+np+SGDnp-cha nnelp+p+ VG VT VG p n n p MaskMaskHigh-velocitydopantionsoI n SourceIon AccelerationMassSeparationBeamSweepingTa rget Chamber MaskMaskHigh-velocitydopantionsM.

6 Nastasi, Mayer: Ion Implantation and Synthesis of Materials (Springer, Berlin, 2006) MOS FET p n MOSFET n p MOSFET IDVDVG=0+VGIDVDVG=0-VG-ID-VDVG=0-VG-ID-V DVG=0+VGn-chanelEnhancementmode(Normally -off)n-chanelDepletionmode(Normally-on)p -chanelEnhancementmode(Normally-off)p-ch anelDepletionmode(Normally-on)00 IDVGIDVG0-IDVG0-IDVGSGDn+pn+SGDpn-channe ln+n+SGDp+np+SGDnp-channelp+p+VDDCLVinVS SGG inputGNDoutputVDDnMOSn-typediffusionp-ty pediffusionn-wellpMOSp-Si+n+n+np+p+n-wel lpoly-Sigaten-wellcontactsourcegateoxide metalSiO2 SiO2n-MOSFETp-MOSFET drainsourcedrainCMOS VOUTVDDVTn0 VDD+VTpVDDNMOSCut-offPMOST riodeNMOSS aturationPMOST riodeNMOSS aturationPMOSS aturationNMOST riodePMOSS aturationNMOST riodePMOSCut-off Marius Grundmann: The Physics of Semiconductors 2nd Ed.

7 (Springer-Verlag, 2010, Berlin) 18,000 1946 ENIAC Electronic Numerical Integrator and Computer ENIAC 10 140kW M. Grundmann, The Physics of Semiconductors 2nd Ed. (Springer, Berlin, 2010) M. Grundmann, The Physics of Semiconductors 2nd Ed. (Springer, Berlin, 2010) ( (1948)) (Fairchild 2N697 (1958)) Ge Si 1420oC Ge SiO2 Si SiO2/Si 938oC GeO2 Ge Q1.

8 Si Ge A. Q2. MOS A. Ge Q3. Ge Si A. SiO2 MOS vs. MOS FET G. S. May and C. J. Spanos: Fundamentals of Semiconductor Manufacturing and Process Control (2006, Wiley, NJ) MOS FET MOSFET D. Kahng: A Historical Perspective on the Development of MOS Transistors and Related Devices, IEEE Trans. Electron Devices, ED-23 (1976) 655-657. F. M. Wanlass: US Patent 3,356,858 (Filed 1963, Issued 1967).

9 CMOS J. E. Lilienfeld: US Patent 1,745,175 (Filed 1926, Issued 1930). FET Oskar Heil: British Patent 439,457 (Filed 1935, issued 1935). MISFET J. Bardeen and W. H. Brattain: US Patent 2,524,035 (Filed 1948, Issued 1950). Dawon Kahng: US Patent 3,102,230 (Filed 1960, Issued 1963). MOSFET MOS E. H. Snow, A. S. Grove, B. E. Deal and C. T. Sah: J. Appl. Phys., 36 (1965) 1664-1673. William H. Miller and Fred Barson: US Patent 3,343,049 (Filed 1964, Issued 1967). Donald R. Kerr and Donald R. Young: US Patent 3,303,059 (Filed 1964, Issued 1967). F. M. Wanlass: US Patent 3,356,858 (Filed 1963, Issued 1967).

10 CMOS Dawon Kahng: US Patent 3,102,230 (Filed 1960, Issued 1963). MOSFET MOS FET MOS FET CMOS CMOS Inverter NAND Gate V1 V2 Vo L L H L H H H L H H H L Vi Vo L H H L Marius Grundmann: The Physics of Semiconductors 2nd Ed. (Springer-Verlag, 2010, Berlin) Intel 4004 (1971) 4004 Busicom Intel Marius Grundmann: The Physics of Semiconductors 2nd Ed. (Springer-Verlag, 2010, Berlin) Intel Pentium 4 ( GHz) Umesh K. Mishra: Semiconductor Device Physics and Design (2008, Springer, Berlin) Moore ID ~ 1/L 64kb 2um 64Mb 64Gb MOS FET SGDn+pn+L MOS Umesh K.