TCG PC Client Specific TIS - trustedcomputinggroup.org

1 TCG TCG PC Client Platform TPM Profile (PTP) Specification Family Level 00 Revision v22 May 22, 2017 Contact: TCG PUBLISHED Copyright TCG 2003 - 2017 TCG PC Client Platform TPM Profile (PTP) Specification Family TCG PUBLISHED Page ii Level 00 Revision v22 Copyright TCG 2003 - 2017 May 22, 2017 Disclaimers, Notices, and License Terms THIS SPECIFICATION IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE. Without limitation, TCG disclaims all liability, including liability for infringement of any proprietary rights, relating to use of information in this specification and to the implementation of this specification, and TCG disclaims all liability for cost of procurement of substitute goods or services, lost profits, loss of use, loss of data or any incidental, consequential, direct, indirect, or special damages, whether under contract, tort, warranty or otherwise, arising in any way out of use or reliance upon this specification or any information herein.

2 This document is copyrighted by Trusted Computing Group (TCG), and no license, express or implied, is granted herein other than as follows: You may not copy or reproduce the document or distribute it to others without written permission from TCG, except that you may freely do so for the purposes of (a) examining or implementing TCG specifications or (b) developing, testing, or promoting information technology standards and best practices, so long as you distribute the document with these disclaimers, notices, and license terms. Contact the Trusted Computing Group at for information on specification licensing through membership agreements. Any marks and brands contained herein are the property of their respective owners. TCG PC Client Platform TPM Profile (PTP) Specification Family TCG PUBLISHED Page iii Level 00 Revision v22 Copyright TCG 2003 - 2017 May 22, 2017 Contents 1 TPM Requirements General Introduction.

3 1 Terminology .. 1 Division of Documentation .. 2 2 Summary of TPM Features to Support the PC Client .. 3 Register Definitions .. 3 Locality .. 3 Interface Type .. 4 Locality Resettable PCRs .. 4 Minimum Amount of NV Storage .. 4 Minimum Number of PCRs .. 4 3 TPM Attributes .. 5 PC Client TPM Minimums and Maximums .. 5 PC Client Algorithms .. 6 PC Client Curves .. 9 Physical Presence .. 9 TPM Handles, Objects and Contexts .. 9 Non-volatile Storage .. 9 NV Storage Size .. 10 General Purpose I/O (GPIO) .. 11 PCR Requirements .. 13 PCR Attributes .. 14 PCR Initial and Reset Values .. 16 Power Management .. 17 Self-Test Requirements .. 18 Firmware Upgrade .. 18 4 TPM Capabilities and Commands .. 20 Command Table .. 20 Locality-Controlled Functions .. 26 DRTM Execution Sequence .. 26 H-CRTM Sequence Before TPM2_Startup() and TPM2_Startup() without H-CRTM .. 31 Timing and Protocol.

4 32 5 TPM Software Interface .. 33 Interface Type .. 33 Locality .. 33 TPM Locality Levels .. 33 Locality Uses .. 35 TPM Register Space .. 36 TPM Register Space Decode .. 36 Register Space Addresses .. 40 System Interaction and Flows .. 45 FIFO Configuration Registers .. 45 Interface Identifier Register .. 46 TPM s Software Interaction .. 54 Interface-Agnostic functions .. 54 FIFO Interface Requirements .. 63 TPM Profile (PTP) Specification TCG PC Client Platform Page iv TCG PUBLISHED Family May 22, 2017 Copyright TCG 2003 - 2017 Level 00 Revision v22 CRB Interface 98 Interrupts .. 120 LPC 121 CRB Interrupts .. 124 6 TPM Hardware .. 127 FIFO Interface Locality Usage per 127 CRB Interface Locality Usage Per Register .. 129 TPM LPC Hardware Protocol .. 130 LPC Locality Cycles for TPM Interface .. 130 SPI Hardware 131 Clocking .. 132 Electrical Specification.

5 133 SPI Interrupts .. 136 Legacy I/O .. 136 Flow 136 SPI Bit Protocol .. 141 TPM Byte Ordering .. 142 Reset Timing .. 143 7 I2C Interface Definition .. 145 TPM I2C Interface Requirements .. 145 Requirements .. 145 Bus speed .. 145 I2C Device address .. 145 Fast turnaround .. 146 Data rate synchronization .. 146 Supply voltage .. 146 Pull-up resistors .. 146 Host interrupt .. 146 Availability after reset .. 147 Locality support .. 147 GUARD_TIME .. 147 Communication Protocol Fundamentals .. 147 Layer Model .. 148 Physical Layer I2C .. 148 Physical Layer TCG-I2C .. 153 Byte 154 Overruns .. 154 Handling of Multi-Byte Registers .. 154 I2C-TPM Localities .. 155 I2C-TPM Registers .. 155 Interface Locality Usage per Register .. 166 TCG-I2C Protocol Usage Scenarios .. 169 8 TPM Hardware Implementation .. 173 TPM Packaging .. 173 Hardware Implementation of a TPM in a PC Client Platform.

6 180 SPI Platform Design Notes .. 181 SW Interface to SPI-TPM .. 181 SW Command Interface to SPI-TPM .. 181 TCG PC Client Platform TPM Profile (PTP) Specification Family TCG PUBLISHED Page v Level 00 Revision v22 Copyright TCG 2003 - 2017 May 22, 2017 9 References .. 183 TPM Profile (PTP) Specification TCG PC Client Platform Page vi TCG PUBLISHED Family May 22, 2017 Copyright TCG 2003 - 2017 Level 00 Revision v22 List of Figures Figure 1 Overview of D-CRTM Measurement Sequence .. 29 Figure 2 PC Client Initialization Sequence .. 59 Figure 3 State Transition Diagram .. 79 Figure 4 TPM State Diagram for CRB Interface .. 115 Figure 5 Timing Diagram .. 135 Figure 6 Clock Timing Diagram .. 136 Figure 7 Example Read transaction with a WAIT state .. 139 Figure 8 Example of WRITE transaction with Wait state .. 140 Figure 9 Layer Model .. 148 Figure 10 Register write sequence on the I2C layer.

7 148 Figure 11 Register write sequence with address NACK on the I2C layer .. 149 Figure 12 Register write sequence with data NACK on the I2C layer .. 150 Figure 13 Register read sequence on the I2C layer .. 151 Figure 14 - Register read sequence on the I2C layer using repeated START (Sr) .. 152 Figure 15 Register read sequence with GUARD_TIME write after read on the I2C layer .. 153 Figure 16 Write / Read TPM_ACCESS register w/o locality selection .. 169 Figure 17 Write / Read TPM_ACCESS register from Locality 0 .. 169 Figure 18 Write / Read TPM_ACCESS register from Locality 0 and 2 .. 170 Figure 19 Read / Write TPM_STS register(s) from Locality 0 .. 171 Figure 20 Read TPM_DATA_FIFO .. 171 Figure 21 Write TPM_DATA_FIFO .. 172 Figure 22 TPM Combo TSSOP-28 Pin Out .. 174 Figure 23 TPM SPI QFN-32 Pin out .. 175 TCG PC Client Platform TPM Profile (PTP) Specification Family TCG PUBLISHED Page vii Level 00 Revision v22 Copyright TCG 2003 - 2017 May 22, 2017 List of Tables Table 1 TPM 5 Table 2 PC Client TPM Algorithms.

8 7 Table 3 TPM Mandatory Curves .. 9 Table 4 PCR Attributes .. 15 Table 5 PCR Initial and Reset Values .. 16 Table 6 Mandatory/Optional TPM Commands .. 20 Table 7 Locality Address Definitions .. 34 Table 8 Relationship between Locality and Locality Attribute .. 35 Table 9 Example Bit-to-Address Mapping .. 39 Table 10 Allocation of Register Space for FIFO and CRB Access .. 40 Table 11 DID/VID Register .. 45 Table 12 RID Register .. 45 Table 13 FIFO Interface Identifier Register .. 46 Table 14 CRB Interface Identifier 49 Table 15 Command Timing .. 57 Table 16 Definition of Interface Timeouts .. 58 Table 17 Allocation of Register Space for FIFO TPM Access .. 63 Table 18 Access 72 Table 19 Status Register .. 81 Table 20 Data FIFO Register .. 91 Table 21 Interface Capability .. 92 Table 22 State Transition Table .. 95 Table 23 Address Allocation for CRB TPM Access.

9 99 Table 24 TPM_LOC_STATE Definition .. 104 Table 25 TPM_LOC_CTRL_x Register Definition .. 105 Table 26 TPM_LOC_CTRL_4 Register Definition .. 106 Table 27 107 Table 28 TPM CRB Control Area Extension .. 108 Table 29 TPM CRB Control Area 109 Table 30 TPM CRB Control Area Status .. 112 Table 31 TPM CRB Control Cancel .. 113 Table 32 TPM CRB Control Start .. 114 Table 33 CRB Interface State Transitions .. 118 Table 34 LPC Interrupt Enable .. 122 Table 35 Interrupt Status .. 123 Table 36 Interrupt Vector .. 124 Table 37 CRB Interrupt Control .. 125 Table 38 Interrupt Status .. 126 Table 39 Register Behavior Based on Locality Setting for 127 Table 40 Register Behavior Based on Locality Setting for CRB .. 129 Table 41 LPC Locality Cycle TPM-Write for Accessing the 131 Table 42 LPC Cycle TPM-Read for Accessing the TPM .. 131 Table 43 DC Specifications for Supply Voltage.

10 134 Table 44 DC Specifications for Supply Voltage .. 134 Table 45 AC Electrical Specifications .. 135 Table 46 SPI Bit Protocol .. 142 Table 47 TPM Locality Selection Register .. 155 Table 48 I2C-TPM Register Overview .. 156 Table 49 TPM Locality Selection Register .. 158 Table 50 Interrupt Enable .. 159 Table 51 Interrupt Capability .. 160 Table 52 Status Register .. 160 Table 53 I2C Interface Capability Register .. 162 Table 54 Data Checksum Enable Register .. 164 Table 55 Data Checksum Register .. 164 TPM Profile (PTP) Specification TCG PC Client Platform Page viii TCG PUBLISHED Family May 22, 2017 Copyright TCG 2003 - 2017 Level 00 Revision v22 Table 56 I2C Device Address Register .. 166 Table 57 Register Behavior Based on Locality Setting for I2C .. 167 Table 58 TSSOP-28 Pin Assignments .. 176 Table 59 TSSOP 28 I2C Pin Assignments .. 178 Table 60 QFN-32 Pin Assignments.