TN-46-05 GENERAL DDR SDRAM FUNCTIONALITY …

1 1 GENERAL DDR SDRAM FunctionalityMicron Technology, Inc., reserves the right to change products or specifications without Rev. A; Pub. 7/01 2001, Micron Technology, DDR SDRAM FUNCTIONALITYGENERAL DDR SDRAMFUNCTIONALITYINTRODUCTIONThe migration from single data rate synchronousDRAM (SDR) to double data rate synchronous DRAM(DDR) memory is upon us. Although there are manysimilarities, DDR technology also provides notableproduct GENERAL , double data rate memory providessource-synchronous data capture at a rate of twice theclock frequency.

2 Therefore, a DDR266 device with aclock frequency of 133 MHz has a peak data transferrate of 266 Mb/s or GB/s for a x64 DIMM. This isaccomplished by utilizing a 2n-prefetch architecturewhere the internal data bus is twice the width of theexternal data bus and data capture occurs twice perclock cycle. To provide high-speed signal integrity, theDDR SDRAM utilizes a bidirectional data strobe,SSTL_2 interface with differential inputs and objective of this technical note is to provide anoverview of the 2n-prefetch architecture, a strobe-baseddata bus, and the SSTL_2 interface used with DDRSDRAM.

3 It will also highlight the functional differencesbetween SDR and the improved DDR memory technol-ogy. For detailed design and timing criteria for DDRSDRAM-based systems, see Micron's DDR SDRAM datasheets.( )Table 1 SDR to DDR Quick ReferenceTable of ContentsDDR vs. SDR 2 Table 1: SDR to DDR Quick 1 Figure 1: Functional Block 2 Figure 4: Example of DDR Command 32n-Prefetch 3 Figure 2: Block Diagram 2n-Prefetch 3 Figure 3: Block Diagram 2n-Prefetch 3 Minimum Time 3 Figure 5: 2n-Prefetch READ Slot Timing.

4 4 Figure 6: 2n-Prefetch WRITE Slot 5 Figure 7: READ Command 6 Strobe-Based Data 4 Preamble and 7 Figure 8: DQS READ Postamble and Preamble .. 7 Figure 9: DQS WRITE Postamble and Preamble . 8 SSTL_2 Interface .. 9 Drivers and 9 Figure 10: Typical LVCMOS 9 Figure 11: Typical SSTL_2 9I/O 10 Figure 12: Typical SSTL_2 Interface andInput 10 clock 11 Figure 13: SSTL_2 11 Summary .. 11 PARAMETERSDRDDRNOTESDQMYesNoUsed for write data mask and read OEDM (Data Mask)NoYesReplaces DQM, used to mask write data onlyDQS (Data Strobe)NoYesNew, used to capture dataCK# (System clock )NoYesNew, DDR utilizes differential clocksVREFNoYesReference voltage for differential inputs (1/2 VDD)

5 VDD and VoltsReduced supply and power for DDRS ignal InterfaceLVTTLSSTL_2 DDR utilizes differential I/OOutput DriveFixedVariablex16 DDR devices offer a reduced drive optionData Rate1x Clock2x ClockData transfer is twice the clock rate for DDRA rchitectureSynchronousSource-Synchronous DDR utilizes a bidirectional data strobeTECHNICALNOTE2 GENERAL DDR SDRAM FunctionalityMicron Technology, Inc., reserves the right to change products or specifications without Rev. A; Pub. 7/01 2001, Micron Technology, DDR SDRAM FUNCTIONALITY12 RAS#CAS#ROW-ADDRESSMUXCKCS#WE#CK#CONTROL LOGICCOLUMN-ADDRESSCOUNTER/LATCHMODE REGISTERS11 COMMAND DECODEA0-A11,BA0, BA1 CKE12 ADDRESSREGISTER141,024(x8)4,096I/O GATINGCOLUMNDECODERBANK0 MEMORYARRAY(4,096 x 1,024 x 8)

6 BANK0 ROW-ADDRESSLATCHANDDECODER4,096 SENSE AMPLIFIERSBANKCONTROLLOGIC12 BANK1 BANK2 BANK312122 REFRESHCOUNTER4441 INPUTREGISTERS1111 RCVRS18828ckoutDATADQSMASKDATACKCKCOL0 COL0 COL0ckinDRVRSDLLMUXDQSGENERATOR444448DQ0 -DQ3, DMDQS1 READLATCHWRITEFIFOANDDRIVERSDQMDQ0-DQ3 4444 DATAINPUTREGISTERDATAOUTPUTREGISTER11 Internal Data Busx4 for SDRx8 for DDRI nternal Data Bus Internal Data Bus (SDR)DQMDQMNot Used for DDR(DDR)DDR I/O InterfaceSDR I/O InterfaceGeneric Memory ArrayNot Used for SDRF igure 1 Functional Block Diagram2 Meg x 4 Memory Array with SDR and DDR InterfaceDDR VS.

7 SDR FUNCTIONALITYSDR SDRAM is well established and generally un-derstood, so questions tend to focus where DDR dif-fers from examination of the 32 Meg x 4 SDR and DDRfunctional block diagrams reveals that the memory coreis essentially the same (see Figure 1). Both have anidentical addressing and command control interface;both have a four-bank memory array; and both incor-porate the same refresh requirements. The fundamen-tal differences are found in the data SDR memory data interface is a fully synchro-nous design where the data is only captured on thepositive clock edge.

8 The internal bus is the same widthas the external data bus and data latches into the inter-nal memory array sequentially as it passes through theI/O buffers. SDR memory also supports a DQM signalthat acts as a data mask during a WRITE operation oran output enable for a DDR memory data is a true source-synchro-nous design, where the data is captured twice per clockcycle with a bidirectional data strobe. This architectureemploys a 2n-prefetch architecture, where the inter-nal data bus is twice the width of the external bus.

9 Thisallows the internal memory cell to pass data to the I/Obuffers in pairs. With DDR, there is no output enablefor READ operations, but DDR does support a BURSTTERMINATE command to quickly end a READ in pro-cess. During a WRITE operation, the DM signal is avail-able to allow the masking of nonvalid write DDR command bus consists of a clock enable,chip select, row and column addresses, bank address,and a write enable as shown in Figure 4. Commands areentered on the positive edges of clock , and data occurson both positive and negative edges of the double data rate memory utilizes a differentialpair for the system clock and therefore will have both atrue clock (CK) and complementary clock (CK#)

10 Positive clock edge for DDR refers to the pointwhere the rising clock signal crosses with the fallingcomplementary clock signal, and the term negativeclock edge indicates the transition of the falling clockand rising complementary clock DDR SDRAM FunctionalityMicron Technology, Inc., reserves the right to change products or specifications without Rev. A; Pub. 7/01 2001, Micron Technology, DDR SDRAM FUNCTIONALITYn-bitDataRegistern-bitDataR egisterCLKDn-bit dataplus DQSQD0 MUXD1 CDQSFromDRAMCore2n-bitdatan-bitdatan-bit dataAll DQand DQSO utputsDQSF igure 2 Simplified Block Diagramof 2n-Prefetch READCS#WE#CAS#RAS#CKECAA10BA0.