TSS721A - M-Bus

1 TSS721 AMETER-BUS TRANSCEIVERSLAS 222 - April 19991 Copyright 1999, Texas Instruments Incorporated Meter-Bus Transceiver(for Slave) meets standard EN1434-3 Receiver logic with dynamic level recognition Adjustable constant current sink via resistor Polarity independent Power fail function Module supply voltage switch V constant voltage source Remote powering Up to 9600 baud in half duplexfor UART protocol Slave Power Support- supply from Meter-Bus via output VDD- supply from Meter-Bus via output VDDor from back up battery- supply from battery Meter-Bus activefor data transmission onlyD PACKAGE(TOP VIEW)

2 BUSL2 STCVBRIDDPFSCTXITXBUSL1 GNDRISRXIRXVDDVSBAT descriptionTSS721A is a single chip transceiver developed for Meter-Bus standard (EN1434-3) TSS721A interface circuit adjusts the different potentials between a slave system and the Meter-Bus master . The connection to the Bus is polarity independent and supports full galvanic slaveisolation with circuit is supplied by the master via the bus. Therefore this circuit offers no additional load for theslave battery. A power-fail function is receiver has dynamic level recognition, and the transmitter a programmable current voltage regulator, with power reserve for a delayed switch off at bus fault, is TRANSCEIVERSLAS 222 - April 19992function (the functional description refers to typical values)Data Transmission master to SlaveThe mark level on the bus lines VBUS= MARK is defined by the difference of BUSL1 and BUSL2at the slave.

3 It is dependent on the distance of master to Slave, which affects the voltage drop onthe wire. To make the receiver independent, a dynamic reference level on the SC pin is used forthe voltage comparator TC3 (refer to figure 1).BRVBBUSL1 GNDBUSL2TC3 TXTXISCISC chargeISCdischargeVTBUSI= constantSPACEMARKV= .. 42 VBUSVBUSITXVTXIVVCSCto ICBUSIMARK=V-10 VBUSL1-BUSL2C= : VB = 25 V; f= 1 MHzmeasFigure 1A capacitor CSCat pin SC is charged by a current ISCchargeand is discharged with a currentISCdischargewhere:This ratio is necessary to run any kind of UART protocol independent of the data contents.

4 (e. g. if an 11-Bit UART protocol is transmitted with all data bits at '0' and only the stop bit at '1').There must be sufficient time to recharge the capacitor CSC. The input level detector TC3 detectsvoltage modulations from the master , VBUS= SPACE/MARK conditions and switches the invertedoutput TXI and the non-inverted output TX.(typ.)SCchargeeSCdischarg40II=TSS721 AMETER-BUS TRANSCEIVERSLAS 222 - April 19993 Data Transmission Slave to MasterThe device uses current modulation to transmit information from Slave to the master while thebus voltage remains constant.

5 The current source CS3 modulates the bus current and the masterdetects the modulation. The constant current source CS3 is controlled by the inverted input RXIor the non-inverted input RX. The current source CS3 can be programmed by an external resistorRRIS. The modulation supply current IMSflows in addition to the current source CS3 during themodulation constantSPACEIMARKIBUSVBUSIRXVRXIVBUSIto ICFigure 2 Since the TSS721A is configured for half-duplex only, the current modulation from RX or RXI isrepeated concurrently as ECHO on the outputs TX and TXI. If the Slave, as well as the master , istrying to send information via the lines, the added signals appear on the outputs TX and TXIwhich indicate the data collision to the slave (refer to figure 6).

6 The bus topology requires a constant current consumption by each connected +=TSS721 AMETER-BUS TRANSCEIVERSLAS 222 - April 19994To calculate the value of the programming resistor RRIS, use the following [mA] [kOhm]0typicalMSMCRIS3 CSRISRISIIV=IV=R VRIS- voltage on pin RISRRIS- programming resistorICS3- programmable currentIMC- modulation currentIMS- modulation supply current(typical 220 A)Figure 3 Slave Supply TSS721A has the voltage regulator. The output power of this voltage regulator issupplied by the storage capacitor CSTCat pin STC. The storage capacitor CSTCat Pin STC ischarged with constant current ISTC_usefrom the current source CS1.

7 The maximum capacitorvoltage is limited to REF1. The charge current ISTChas to be defined by an external resistor atPin adjustment resistor RRIDDcan be calculated using the following formula:1 CISTC_useRIDDSTCRIDDRIDDIIV25=IV25=R+IST C- current from current source CS1 ISTC _use- charge current for support capacitorICI- internal currentVRIDD- voltage on pin RIDDRRIDD- value of adjustment resistorTSS721 AMETER-BUS TRANSCEIVERSLAS 222 - April 19995 The voltage level of the storage capacitor CSTCis monitored with comparator TC1. Once thevoltage VSTC reaches VVDD_on, the switch SVDD connects the stabilised voltage VVDDto pin turned off if the voltage VSTC drops below the variations on the capacitor CSTC create bus current changes:916 IBUS3914910912[A]4567 VSTC[V]8 Example: Single Mode Bus Load12 Figure 4At a bus fault the shut down time of VDD(toff) in which data storage can be performed depends onthe system current IVDDand the value of capacitor CSTC.

8 Refer to Figure 5, which shows acorrelation between the shut down of the bus voltage VBUSand VDD_offand tofffor dimensioningthe output VS is meant for slave systems which are driven by the bus energy, as well as from abattery should the busline voltage fail. The switching of VS is synchronised with VDDand iscontrolled by the comparator TC1. An external transistor at the output VS allows switching fromthe Meter-Bus remote supply to TRANSCEIVERSLAS 222 - April 19996 POWER ON-OFFVBV=VontDDonVBUSVSTCVVSVSTC+ threshold voltagefor power fail PFtttttFigure 5 Power Fail FunctionOwing to the rectifier bridge BR at the input, BUSL1 and BUSL2, the TSS721A is polarityindependent.

9 The pin VB to ground (GND) delivers the bus voltage VVBless the voltage drop overthe rectifier BR. The voltage comparator TC2 monitors the bus voltage. If the voltage VVB>VSTC+ V, then the output PF = '1'. The output level PF = '0' (power fail) provides a warning ofa critical voltage drop to the microcontroller to save the data + =TSS721 AMETER-BUS TRANSCEIVERSLAS 222 - April 19997functional 6pinningpinfunction1 BUSL2 Meter-Bus2 VBdifferential bus voltage after rectifier3 STCsupport capacitor4 RIDD current adjustment input5 PFpower fail output6 SCsampling capacitor7 TXIdata output inverted8 TXdata output9 BATlogic level adjust10 VSswitch for bus or battery supply output11 VDDvoltage regulator output12 RXdata input13 RXIdata input inverted14 RISadjust input for modulation current15 GNDground16 BUSL1

10 Meter-BusTSS721 AMETER-BUS TRANSCEIVERSLAS 222 - April 19998absolute maximum ratingsVoltage BUSL1 to BUSL2|50| VInput voltage at RX and RXI- to VInput voltage at pin UBAT- to VOperating junction temperature- 25 to 150 COperating temperature free-air- 25 to 85 CStorage temperature- 65 to 150 CPower derating factor junction to mW/ Crecommended operating conditionsParameterminmaxunitBus |BUSL2-BUSL1| (receive mode) RISR esistor100 VBAT, (seeNote1) free-air temperature-2585 CNOTE:All voltage values are measured with respect to the GND terminal unless otherwise 1: VBATmax <=VSTC 1 VTSS721 AMETER-BUS TRANSCEIVERSLAS 222 - April 19999electrical characteristics at recommended ranges(unless otherwise noted)ParameterTest conditionsmintypmaxunitVdropRectifier BRIBUS= drop currentsource CS1 RIDD=13 k V; IMC=0 mARIDD=13 k V; IMC=0 mARIDD=30 k IBUS VBUS=10 V; IMC=0 mARIDD=13 30k 2%ICCVSTC= V; IMC=0 mA; VBAT= V;RIDD=13 k ; (seeNote2)650 AICI1 VSTC= V; IMC=0 mA; VBAT= V;RIDD=13 k ;VBUS= V.