UC3842/UC3843/UC3844/UC3845 SMPS Controller

1 2002 Fairchild Semiconductor Low Start up Current Maximum Duty Clamp UVLO With Hysteresis Operating Frequency up to 500 KHzDescriptionThe UC3842/UC3843/UC3844/UC3845 are fixedfrequencycurrent-mode PWM Controller . They are specially designed for Off-Line and DC to DC converter applications with minimum external components. These integrated circuits feature a trimmed oscillator for precise duty cycle control, a temperature compensated reference, high gain error amplifier, current sensing comparator and a high current totempole output for driving a Power MOSFET.

2 The uc3842 and uc3844 have UVLO thresholds of 16V (on) and 10V (off). The uc3843 and uc3845 are (on) and (off). The uc3842 and uc3843 can operate within 100% duty cycle. The uc3844 and uc3845 can operate with 50% duty Block DiagramUC3842/ uc3843 / uc3844 / uc3845 SMPS Controller * NORMALLY 8 DIP/8 SOP PIN NO.* ( ) IS 14 SOP PINNO.* TOGGLE FLIP FLOP USED ONLY IN uc3844 , UC3845UC3842/ uc3843 / uc3844 /UC38452 Absolute Maximum RatingsNote:1. Board Thickness , Board Dimension , (Reference EIA / JSED51-3, 51-7)2. Do not exceeed PD and SOA (Safe Operation Area)Power Dissipation CurveThermal DataPin ArrayParameterSymbolValueUnitSupply VoltageVCC30 VOutput CurrentIO 1 AAnalog Inputs (Pin )V(ANA) to Amp Output Sink CurrentISINK ( )10mAPower Dissipation at TA 25 C (8 DIP)PD(Note1,2)1200mWPower Dissipation at TA 25 C (8 SOP)PD(Note1,2)460mWPower Dissipation at TA 25 C (14 SOP)PD(Note1,2)680mWStorage Temperature RangeTSTG-65 ~ +150 C Lead Temperature (Soldering, 10sec)TLEAD+300 C CharacteristicSymbol8-DIP8-SOP14-SOPUnit Thermal Resistance Junction-ambientRthj-amb(MAX)

3 100265180 C/W800700600500400300900100011000 1020304050 60708090100110120130140150 AMBIENT TEMPERATURE ( C)POWER DISSIPATION (mW)12008 DIP14 SOP8 SOP800700600500400300900100011000 102030405030405060708060708090100 11090100 110 120 130 140120 130 140 150 AMBIENT TEMPERATURE ( C)POWER DISSIPATION (mW)12008 DIP14 SOP8 SOPVCCGNDPWR GNDCOMP1N/C2 VFBN/C34 VREFN/CPWR VC14131211 CURRENT SENSE5N/CRT/CT67 OUTPUT1098 COMP1 VFB2 CURRENT SENSERT/CT34 VREFVCCOUTPUTGND87658 DIP,8 SOP14 SOPVCCGNDPWR GNDCOMP1N/C2 VFBN/C34 VREFN/CPWR VC14131211 CURRENT SENSE5N/CRT/CT67 OUTPUT1098 VCCGNDPWR GNDCOMP1N/C2 VFBN/C34 VREFN/CPWR VC14131211 CURRENT SENSE5N/CRT/CT67 OUTPUT1098 COMP1 VFB2 CURRENT SENSERT/CT34 VREFVCCOUTPUTGND8765 COMP1 VFB2 CURRENT SENSERT/CT34 VREFVCCOUTPUTGND87658 DIP,8 SOP14 SOPUC3842/ uc3843 / uc3844 /UC38453 Electrical Characteristics(VCC=15V, RT=10k , CT= , TA= 0 C to +70 C.)

4 Unless otherwise specified) SECTIONR eference Output VoltageVREF TJ = 25 C, IREF = Regulation VREF 12V VCC 25V-620mVLoad Regulation VREF 1mA IREF 20mA-625mVShort Circuit Output CurrentISC TA = 25 C--100-180mAOSCILLATOR SECTIONO scillation Frequencyf TJ = 25 C475257kHzFrequency Change with Voltage f/ VCC 12V VCC AMPLIFIER SECTIONI nput Bias AInput VoltageVI(E>A) Vpin1 = Loop Voltage GainGVO 2V VO 4V (Note3)6590-dBPower Supply Rejection RatioPSRR 12V VCC 25V (Note3)6070-dBOutput Sink CurrentISINK Vpin2 = , Vpin1 = Source CurrentISOURCE Vpin2 = , Vpin1 = Output VoltageVOH Vpin2 = , RL = 15k to GND56-VLow Output VoltageVOL Vpin2 = , RL = 15k to Pin SENSE SECTIONGainGV (Note 1 & 2) Input SignalVI(MAX) Vpin1 = 5V(Note 1) Supply Rejection RatioPSRR 12V VCC 25V (Note 1,3)-70-dBInput Bias CurrentIBIAS---3-10 AOUTPUT SECTIONLow Output Voltage VOL ISINK = ISINK = Output Voltage VOH ISOURCE = ISOURCE = TimetR TJ = 25 C, CL= 1nF (Note 3)-45150nsFall TimetF TJ = 25 C, CL= 1nF (Note 3)

5 -35150nsUNDER-VOLTAGE LOCKOUT SECTIONS tart Threshold VTH(ST) uc3842 Operating Voltage(After Turn On)VOPR(MIN) uc3842 uc3843 Characteristics (Continued)(VCC=15V, RT=10k , CT= , TA= 0 C to +70 C, unless otherwise specified)Adjust VCC above the start threshould before setting at 15 VNote:1. Parameter measured at trip point of latch 2. Gain defined as:3. These parameters, although guaranteed, are not 100 tested in 1. Open Loop Test CircuitHigh peak currents associated with capacitive loads necessitate careful grounding techniques Timing and bypass capacitors should be connected close to pin 5 in a single point ground.

6 The transistor and 5k potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to pin SECTION Max. Duty Cycle D(Max) uc3842 /UC38439597100%D(Max) uc3844 /UC3845474850%Min. Duty CycleD(MIN)---0%TOTAL STANDBY CURRENTS tart-Up Supply CurrentICC(OPR) Vpin3=Vpin2=ON-1417mAZener VoltageVZ ICC = 25mA3038-VA Vpin1 Vpin3------------------= uc3842 ,0 Vpin3 2. Under Voltage LockoutDuring Under-Voltage Lock-Out, the output driver is biased to a high impedance state. Pin 6 should be shunted to ground with a bleeder resistor to prevent activating the power switch with output leakage 3.

7 Error Amp ConfigurationFigure 4. Current Sense CircuitPeak current (IS) is determined by the formula:A small RC filter may be required to suppress switch () 5. Oscillator Waveforms and Maximum Duty CycleOscillator timing capacitor, CT, is charged by VREF through RT and discharged by an internal current source. During the discharge time, the internal clock signal blanks the output to the low state. Selection of RT and CT therefore determines bothoscillator frequency and maximum duty cycle. Charge and discharge times are determined by the formulas:tc = RT CTFrequency, then, is: f=(tc + td)-1 Figure 8.

8 Shutdown TechniquesFigure 6. Oscillator Dead Time & FrequencyFigure 7. Timing Resistance vs ---------------------------------------- =ForRT 5K ,>(Deadtime vs CT RT > 5k ) uc3842 / uc3843 / uc3844 /UC38457 Shutdown of the uc3842 can be accomplished by two methods; either raise pin 3 above 1V or pull pin 1 below a voltage two diode drops above ground. Either method causes the output of the PWM comparator to be high (refer to block diagram). The PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shutdown condition at pins 1 and/or 3 is removed.

9 In one example, an externally latched shutdown may be accomplished by adding an SCR which will be reset by cycling VCC below the lower UVLO threshold. At this point the reference turns off, allowing the SCR to 9. Slope CompensationA fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope compensation for converters requiring duty cycles over 50%. Note that capacitor, CT, forms a filter with R2 to suppress the leading edge switch ( C)Figure 10. Temperature Drift (Vref) Temperature ( C)Figure 11. Temperature Drift (Ist) Temperature ( C)Figure 12.

10 Temperature Drift (Icc) uc3842 /UC3843UC3842/ uc3843 / uc3844 / uc3845 8 Mechanical #1#4#5# () ~15 + + Dimensions (Continued) ~ ~ #1#4#50~8 # () + + Dimensions (Continued) #1#7#80~8 # () + + + + InformationProduct NumberPackageOperating TemperatureUC3842N 8-DIP0 ~ + 70 CUC3843 NUC3844 NUC3845 NUC3842D1 8-SOPUC3843D1UC3844D1UC3845D1UC3842D 14-SOPUC3843D UC3844D UC3845D uc3842 / uc3843 / uc3844 /UC38452/19/02 001 Stock#DSxxxxxxxx 2002 Fairchild Semiconductor CorporationLIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION.