UltraFast Design Methodology Guide for the …

1 UltraFast Design Methodology Guide for the Vivado Design Suite UG949 ( ) November 23, 2015 Starting with the version of the Vivado Design Suite (June 8, 2016), this document is beingStarting with the version of the Vivado Design Suite (June 8, 2016), this document is beingStarting with the version of the Vivado Design Suite (June 8, 2016), this document is beingStarting with the version of the Vivado Design Suite (June 8, 2016), this document is beingupdated at a new web location. Click this updated at a new web location. Click this updated at a new web location. Click this updated at a new web location. Click this linklinklinklink to navigate to the latest version. to navigate to the latest version.

2 To navigate to the latest version. to navigate to the latest Design Methodology ( ) November 23, 2015 Revision HistoryThe following table shows the revision history for this document . DateVersionRevision11/23 Using IP Core Containers, updated Logic Simulation, added information on core container files to in Recommended Source Files to Manage, Minimum Sets of Source Files to Manage, and Vivado Design Suite Source Types, added information on core containers in Managing IP Sources in Chapter 2, Using the Vivado Design Ta b l e 3-1, added SLR Utilization Considerations, and added SLR Crossing for Wide Buses in Chapter 3, Board and Device UltraScale Device Clocking and updated Pipelining Considerations in Chapter 4, Design information on report_design_analysis in Clock Skew and Uncertainty in Chapter 5, Figure and updated Chapter 2, Using the Vivado Design Suite.

3 Including adding new Source Management and Revision Control Recommendations I/O Planning Design Flows in Chapter 3, Board and Device and updated Chapter 4, Design Timing Closure in Chapter 5, Implementation, including moving common Design bottlenecks information to the Vivado Design Suite User Guide : Design Analysis and Closure Techniques (UG906).Reorganized and updated Chapter 6, Configuration and Debug, including adding links to various additional IP Flows related sections. Minor fixes/clarifications based on specific power section. Major revamp of Vivado Design Suite Flows , and Configuration and Debug chapters. Fixed specific typos, heading name/levels and minor checklist appendix.

4 These links have been replaced with a checklist version that is available in Documentation Navigator. 11/25 errors in table of incorrect xilinx FeedbackUltraFast Design Methodology ( ) November 23, 2015 table of ContentsChapter 1: IntroductionAbout This Guide .. 5 Guide Contents.. 5 Guide Applicability and References .. 6 Need for Design Methodology .. 6 Design Methodology Checklist .. 7 Design Process .. 8 Rapid Validation.. 11 Accessing Documentation and Training .. 12 Chapter 2: Using the Vivado Design SuiteOverview of Using the Vivado Design Suite .. 15 Vivado Design Suite Use Models.. 19 Configuring IP .. 23 Creating IP Subsystems with IP Integrator .. 28 Packaging Custom IP and IP Subsystems.

5 32 Creating Custom Peripherals.. 33 Logic Simulation .. 34 Synthesis, Implementation, and Design Analysis .. 43 Source Management and Revision Control Recommendations .. 43 Upgrading Designs and IP to the Latest Vivado Design Suite Release .. 60 Chapter 3: Board and Device PlanningOverview of Board and Device Planning .. 62 PCB Layout Recommendations .. 62 Clock Resource Planning and Assignment .. 65I/O Planning Design Flows.. 67 FPGA Power Aspects and System Dependencies .. 87 Worst Case Power Analysis Using xilinx Power Estimator (XPE) .. 98 Configuration .. 102 Chapter 4: Design CreationOverview of Design Creation.. 104 Send FeedbackUltraFast Design Methodology ( ) November 23, 2015 Defining a Good Design Hierarchy.

6 105 RTL Coding Guidelines .. 108 Clocking Guidelines .. 157 Working With Intellectual Property (IP).. 204 Working with Constraints .. 210 Chapter 5: ImplementationOverview of Implementation .. 255 Synthesis.. 255 Synthesis Attributes.. 259 Bottom Up Flow .. 261 Moving Past Synthesis .. 263 Implementing the Design .. 266 Timing Closure .. 280 Power .. 327 Chapter 6: Configuration and DebugOverview of Configuration and Debug .. 338 Configuration .. 338 Debugging.. 344 Appendix A: Baselining and Timing Constraints Validation ProcedureIntroduction .. 358 Procedure .. 358 Appendix B: Additional Resources and Legal NoticesXilinx Resources .. 360 Solution Centers.

7 360 References .. 360 Training Resources .. 363 Please Read: Important Legal Notices .. 363 Send FeedbackUltraFast Design Methodology ( ) November 23, 2015 Chapter 1 IntroductionAbout This GuideXilinx programmable devices have capacities of multi-million Logic Cells (LC), and integrate an ever-increasing share of today s complex electronic systems, including: Embedded subsystems Analog and digital processing High-speed connectivity Network processingIn order to create such complex systems within short Design cycles, designers synthesize many large blocks of logic from RTL, and reuse Intellectual Property (IP) modules from xilinx or third the complexity of this process, it is critical to adopt a set of best practices collectively called the UltraFast Design Methodology , a set of best practices that maximize productivity for both system integration and Design ContentsThis Guide discusses a Design Methodology process to follow in order to achieve an efficient and quicker Design implementation, and to derive the maximum value from xilinx devices and most cases, this Guide tells you the reasoning behind its recommendations.

8 By understanding that reasoning, you can appreciate the potential consequences of deviating from the recommended Methodology , and take appropriate FeedbackUltraFast Design Methodology ( ) November 23, 2015 Chapter 1: IntroductionGuide Applicability and ReferencesAlthough this Guide is primarily for use with the xilinx Vivado Design Suite, most of the conceptual information in this Guide can be leveraged for use with the xilinx ISE Design Suite as well. This Guide provides high-level information, Design guidelines, and Design decision Guide includes references to other documents such as the Vivado Design Suite User Guides, Vivado Design Suite Tutorials, and Quick-Take Video Tutorials. This Guide is not a replacement for those documents.

9 You should still refer to those documents for detailed, current information, including descriptions of tool use and Design Methodology . For a more complete listing of reference documents, see Appendix B, Additional Resources and Legal various places, the Guide gives the Vivado tools command for a specific task. Run the command with -help for detailed information (including example usage).Need for Design MethodologyAdvanced algorithms used in today s increasingly complex electronic products are stretching the boundaries of density, performance, and power. This creates many challenges for the Design teams to hit the target release window within their allocated budget. The UltraFast Design Methodology allows project managers to: Accelerate time to market, thus increasing product revenue and market share.

10 Formulate an accurate estimate of the project schedule and cost, reducing Guide is a collection of best practices covering aspects related to board planning, Design creation, IP integration, Design implementation and closure techniques, programming, and hardware debug. These best practices and recommendations have been gathered from a large pool of expert users over the past several years. The recommendations in this Guide will help you succeed as they have for many of xilinx Design Suite is also automating part of the UltraFast Design Methodology by providing: DRC rules that provide guidance on HDL code and XDC constraints so engineers can improve the quality of their Design earlier in the flows and avoid problems downstream when iterations would be costlier.