UltraScale Architecture SelectIO Resources - Xilinx

1 UltraScale Architecture SelectIO ResourcesUser Guide UG571 ( ) June 12, 2018 UltraScale Architecture SelectIO Resources2UG571 ( ) June 12, HistoryThe following table shows the revision history for this document. DateVersionRevision06/12 1, SelectIO Interface Resources . Updated DQS_BIAS. Starting with Vivado Design Suite , the DQS_BIAS attribute must be set on the port, not on the cell. Added notes that drivers and receivers must be at the same voltage level. Added the last row (OUTPUT_IMPEDANCE) to Table 1-48. Deleted Figure 2-20: COUNT Mode with Fast Updates.

2 Chapter 2, SelectIO Interface Logic Resources . Updated Table 2-4. Clarified reserved bits and defaults in Table 2-39 through Table 3, High Density I/O Resources . Added the ZHOLD heading. Updated DDR Outputs (ODDRE1).02/07 Chapter 2, updated BITSLICE and waveform information. Updated Figure 2-2, Figure 2-12, Figure 2-13, Figure 2-15, and Figure 2-20. Changed RXTX_BITSLICE to ISERDES in Figure 2-20. Added Count mode with fast update information and Figure 2-22. Updated Figure 2-20 and Figure 2-25. Updated Figure 2-37, Figure 2-40, and Figure 2-41.

3 The Values and Description changed in Table 2-18. The Component Mode Reset Sequence was updated. Added Table 2-19, Bidirectional Support by I/O Bank. Updated Caution on page 310 and Tip on page 311. Updated Caution on page 320. Updated Table 2-22 for ports RX_RST and FIFO_RD_EN and TX_RST. Updated Table 2-22 attribute RX_REFCLK_FREQUENCY and TX_REFCLK_FREQUENCY. Updated Table 2-24 port RST. Updated Table 2-26 port RST. Updated Table 2-28 port RST. Updated Table 2-29 attribute REFCLK_FREQUENCY. Updated the REFCLK port and BITSLICE_CONTROL port REFCLK in Table 2-30.

4 Updated the REFCLK_SRC attribute and BITSLICE_CONTROL attribute in Table 2-31. Updated Table 2-38 port RIU_WR_EN. Updated Table 2-40, Table 2-58, and Table FeedbackUltraScale Architecture SelectIO Resources3UG571 ( ) June 12, book was updated for UltraScale and UltraScale + devices. The SIM_DEVICE attribute was added to several bit slice attribute 2: Extensive clarifications were made, including clarifications for BITSLICE_0 restrictions. Updated delay line procedures when multiple updates are required for component primitives and native primitives.

5 For component primitives, updated primitive port descriptions and attributes. For native primitives, updated primitive port descriptions and , added IS_C_INVERTED, IS_CB_INVERTED in Table 2-2. Added IS_D1_INVERTED, IS_D2_INVERTED in Table 2-4. Added waveforms to describe latencies (Figure 2-12, Figure 2-13). Updated CLK_B description (Table 2-6). Added IS_CLK_INVERTED, IS_CLK_B_INVERTED, IS_RST_INVERTED and SIM_DEVICE (Table 2-7). Added OSERDES latency (Figure 2-14). Updated T description in Table 2-9. Added IS_CLK_INVERTED, IS_CLKDIV_INVERTED, IS_RST_INVERTED, and SIM_DEVICE (Table 2-10).

6 Updated REFCLK_FREQUENCY requirements for TIME mode in the IDELAYE3 section. Updated descriptions for RST, EN_VTC, DELAY_VALUE, and DELAY_FORMAT (Table 2-12). Added SIM_DEVICE (Table 2-12). Updated delay procedures for updating VARIABLE and VAR_LOAD to describe multiple updates (DELAY_TYPE descriptions in IDELAY, ODELAY, and Native Input Delay Type Usage). Updated descriptions for RST and EN_VTC (Table 2-15). Updated DELAY_VALUE for UltraScale + devices (Table 2-16). Added SIM_DEVICE (Table 2-16). Updated Variable Mode waveform (Figure 2-24) for multiple updates.

7 Added Table 2-18. Removed DELAY_TYPE=FIXED from Component Mode Reset Sequence. Updated Figure 2-26 to show BUFGCE_DIV usage from a single MMCM clock. Added MMCM descriptions for clock outputs and Figure 2-27. Updated REFCLK_FREQUENCY requirements in Mixing Native and Non-Native Mode I/O in a Nibble. Added latency wafeforms for RX_BITSLICE (Figure 2-37, Figure 2-38) and TX_BITSLICE (Figure 2-40, Figure 2-41,). Updated Figure 2-42 for multiple updates. Updated descriptions and added TX_OUTPUT_PHASE_90 restriction for Table 2-23. Added UltraScale + device values and added SIM_DEVICE to Table 2-23.

8 Added UltraScale + device values for Table 2-25. Added SIM_DEVICE to Table 2-25. Updated T, TBYTE_IN descriptions for Table 2-26. Added UltraScale + device values for Table 2-27. Added TX_OUTPUT_PHASE_90 restriction for Table 2-27. Added latency figures for TX_BITSLICE_TRI (Figure 2-56, Figure 2-57), Added UltraScale + device values and TX_OUTPUT_PHASE_90 restriction for Table 2-29. Added SIM_DEVICE (Table 2-29, Table 2-31). Highlighted strobe operation during reset sequence should either be held in reset (updated Figure 2-60) or bitslip is required.

9 Added Native Mode Bring-up when using multiple banks and when a bank uses multiple interfaces. Added SIM_DEVICE to Table 2-23. Added RIU Registers 0x37, 0x38, and 0x39 (Table 2-58,Table 2-59, and Table 2-60).DateVersionRevisionSend FeedbackUltraScale Architecture SelectIO Resources4UG571 ( ) June 12, 1: Updated DCI Only Available in the HP I/O Banks. Updated sections in Uncalibrated Input Termination in I/O Banks, IBUF_IBUFDISABLE, IBUF_INTERMDISABLE, IBUFDS_DIFF_OUT_IBUFDISABLE, IBUFDS_DIFF_OUT_INTERMDISABLE and many more. Chapter 2: This chapter was rewritten for clarification.

10 In the Component Primitives section, replaced IDELAY_CTRL with IDELAYCTRL. Reorganized Native Primitives section and updated sub-sections with many clarifications. Added Synchronous Clock Domain columns to port tables Table 2-22, Table 2-24, Table 2-26, and Table :Because the new Chapter 2 organization changed or deleted previous figure and table numbers, references in subsequent rows of this revision history table were accurate as of the date the version was printed. Chapter 3: Updated HD I/O Bank Features and HD I/O Interface the Virtex UltraScale + family, the Kintex UltraScale + family, and Zynq UltraScale + MPSoCs to this user 1: Added IBUFDS_DPHY, OBUFDS_DPHY, and MIPI D-PHY sections.