Universal Verification Methodology (UVM) 1.1 …

1 Universal Verification Methodology (UVM) user s GuideMay 18, 2011iiUVM user s GuideMay 18, 2011 Copyright 2011 Accellera. All rights 2011 Cadence Design Systems, Inc. (Cadence). All rights Design Systems, Inc., 2655 Seely Ave., San Jose, CA 95134, 2011 Mentor Graphics, Corp. (Mentor). All rights Graphics, Corp., 8005 SW Boeckman Rd., Wilsonville, OR 97070, USAC opyright 2011 Synopsys, Inc. (Synopsys). All rights , Inc., 700 E. Middlefield Rd, Mountain View, CA 94043 This product is licensed under the Apache Software Foundation s Apache License, Version , January 2004. The full license is available at: this guide offers a set of instructions to perform one or more specific Verification tasks, it should besupplemented by education, experience, and professional judgment.

2 Not all aspects of this guide may beapplicable in all circumstances. The UVM user s guide does not necessarily represent the standard ofcare by which the adequacy of a given professional service must be judged nor should this document beapplied without consideration of a project s unique aspects. This guide has been approved through theAccellera consensus process and serves to increase the awareness of information and approaches inverification Methodology . This guide may have several recommendations to accomplish the same thing andmay require some judgment to determine the best course of UVM Class Reference represents the foundation used to create the UVM user s guide . Thisguide is a way to apply the UVM Class Reference, but is not the only way.

3 Accellera believes standardsare an important ingredient to foster innovation and continues to encourage industry innovation based on for improvements to the UVM user s guide are welcome. They should be sent to the VIPemail reflector current Working Group s website address May 18, 2011 UVM user s to Verification (CDV) .. and Environments .. Component Item (Transaction) .. (BFM) .. UVM Class UVM Factory .. Modeling (TLM) .. Modeling (TLM) .. , TLM-1, and .. Implementation .. Implementation .. Communication .. TLM Communication .. between Processes .. versus Nonblocking .. Transaction-Level Components .. connections .. Compatibility .. and Hierarchy .. Connections .. Types .. Communication.

4 Ports .. Exports .. Payload .. Interfaces and Ports .. Transport .. Sockets .. Time .. Use 28ivUVM user s GuideMay 18, Reusable Verification Data Items for Generation .. and Constraint Layering .. Control Fields ( Knobs ) .. Components .. the the Connecting the Driver and Sequencer and Driver Interaction .. for the Randomized Item .. Consecutive Randomized Items .. Processed Data back to the Sequencer .. TLM-Based Drivers .. the Monitor .. the Agent .. Modes .. Components .. the Environment .. Environment Class .. UVM Configuration Mechanism .. Enabling Scenario user -Defined Sequences .. Stimulus with Sequences and Sequence Items .. the Sequencer s Default Sequence.

5 Sequence Items and Sequences .. Managing End of Test .. Implementing Checks and Checks and Coverage in Classes .. Checks and Coverage in Interfaces .. Checks and Coverage .. Verification Components .. a Verification Verification Components .. Class .. Component Configuration .. Component Configurable Parameters .. Component Configuration Mechanism .. between uvm_resource_db and uvm_config_db .. a Configuration Class .. and Selecting a user -Defined Test .. the Base Test .. Tests from a Test-Family Base Class .. Selection .. Meaningful Tests .. Data Items .. Item Definitions .. a Test-Specific Frame .. 68 May 18, 2011 UVM user s a Virtual Sequencer .. a Virtual Sequence .. Other Sequencers.

6 A Virtual Sequencer to Subsequencers .. for DUT Scoreboards .. the Scoreboard .. Exports to uvm_scoreboard .. of the TLM Implementation .. the Action Taken .. the Scoreboard to the Environment .. Implementing a Coverage Model .. a Coverage Method .. a Functional Coverage Model .. and Disabling Coverage .. the Register Layer Classes .. Model .. Access .. are not Mirrored .. API .. / write .. / poke .. / set .. Accesses .. Coverage Identifiers .. Coverage Model Construction and Sampling .. a Register Types .. Types .. File Types .. Types .. Types .. a Register Model .. Data Size .. read/write vs. peek/poke .. HDL Paths .. Back-door Access .. Back-door Access .. Access for Protected Memories.

7 Monitoring .. Registers .. Special Registers .. Registers and Memories .. 112viUVM user s GuideMay 18, Registers .. Registers .. and WO Registers Sharing the Same Address .. a Register Model in a Verification a Register Adapter .. Bus Sequencers .. the Register Model with a Bus Monitor .. Randomizing Field Values .. Pre-defined Sequences .. Topics .. uvm_component Base Class .. Built-In Factory and Overrides .. the Factory .. Registration .. Overrides .. Model .. Sequence Library .. Sequence Control .. Complex Scenarios .. Layering .. the Item or Sequence in Advance .. Sequences and Items on other Sequencers .. Line Interface (CLI).. Started .. Command Line Processing .. Verification Component Example.

8 Example Top Module .. Environment .. Master Agent .. Master Sequencer .. Driver .. UBus Agent Monitor .. UBus Bus Monitor .. Transfers from the Bus .. of Transfers .. Emitted by the UBus Bus Monitor .. and Coverage .. UBus 172 May 18, 2011 UVM user s Specification .. Overview .. Description .. Signals .. Phase .. Cycle .. Address Phase .. Phase .. Transfer .. during Write Transfer .. Transfer .. during Read Transfer .. Data is Pipelining Arbitration Phase .. Address Phase .. Data Phase .. Timing Diagrams .. 178 Appendix A (informative) Sequence Library .. the Sequencer .. Scenario Creation .. 182viiiUVM user s GuideMay 18, 2011 May 18, 2011 UVM user s Guide11. OverviewThis chapter describes: How to use the Universal Verification Methodology (UVM) for creating SystemVerilog testbenches.

9 The recommended architecture of a Verification Introduction to UVMThe following subsections describe the UVM Coverage-Driven Verification (CDV)UVM provides the best framework to achieve coverage-driven Verification (CDV). CDV combinesautomatic test generation, self-checking testbenches, and coverage metrics to significantly reduce the timespent verifying a design. The purpose of CDV is to: Eliminate the effort and time spent creating hundreds of tests. Ensure thorough Verification using up-front goal setting. Receive early error notifications and deploy run-time checking and error analysis to simplify CDV flow is different than the traditional directed-testing flow. With CDV, you start by settingverification goals using an organized planning process.

10 You then create a smart testbench that generateslegal stimuli and sends it to the DUT. Coverage monitors are added to the environment to measure progressand identify non-exercised functionality. Checkers are added to identify undesired DUT are launched after both the coverage model and testbench have been implemented. Verificationthen can be CDV, you can thoroughly verify your design by changing testbench parameters or changing therandomization seed. Test constraints can be added on top of the smart infrastructure to tune the simulation tomeet Verification goals sooner. Ranking technology allows you to identify the tests and seeds that contributeto the Verification goals, and to remove redundant tests from a test-suite environments support both directed and constrained-random testing.