VCE405 Connectivity Engine - acoutronic.se

1 VCE405 Connectivity Engine > Single-Board Computerwith Ultra Low Power Consumption> 400 MHz PowerPC 405 GPr Engine > Draws less than 7 Watts of Power> 128 MB SDRAM, 8 MB Flash, CompactFlash Socket> Ethernet 10/100 BASE-T; IIC Port; 6 Serial Lines> 2 PMC Slots> Capable of Running with Natural Convection Only> Supports VxWorks, LynxOS , and Linux2 PowerPC 405GP/GPrThe IBM PowerPC 405GP is a32-bit RISC embedded performance and peripheralintegration of the 405GP/GPrmake the device ideal for wiredcommunications and other perva-sive computing 405GP/GPr is powered by aPowerPC 405B3 embedded core tightly couples either a266 MHz CPU and 24 KB datacache (16 KB I-cache; 8 KB D-cache) for the PowerPC 405GP ora 400 MHz and 32 KB data cache(16 KB I-cache.)

2 16 KB D-cache) forthe PowerPC 405 GPr. This finely-tuned core reduces data transferoverhead and minimizes pipelinestalls to greatly improve general architecture of the405GP/GPr consists of a 64-bit,133 MHz Processor Local Bus(PLB) and a 32-bit, 44 MHz On-ChipPeripheral Bus (OPB).High-performance peripheralsattach to the PLB and less per-formance-critical peripherals attachto the ClockThe Real-Time Clock (RTC) function isprovided by a Dallas SemiconductorDS1602 Elapsed Time device can keep track of over125 years worth of seconds in eachof its 32-bit counters.

3 One counterruns continuously. The other counter counts secondsonly while +5V is active. Softwarecan determine how long the RTChas been running on battery powerby subtracting the VCC active count-er from the continuous 128 MB SDRAM The system memory consists of twobanks of 64 MB yielding, 128 MBof synchronous DRAM with ErrorControl and Correction. TheSDRAM is directly controlled by theprocessor using a 32-bit, 133 version featuring the PowerPC405GP at 266 MHz and only 64MB is also MB Flash EPROMIn addition, the board provides oneFlash memory array which is com-posed of two equal-sectored Intel28F320-J5a-110, 2M x 16 FlashEPROMs for a total of 8 MB.

4 EachEPROM has 32 128 kB blocks, butsince the EPROMs are concatenat-ed to form a 32-bit data path, thepaired EPROM block size is 256 Computers uses the lowestaddressed blocks for its test andboot software and for storing theEPROM's programming blocks are then locked intothe array so they cannot be acci-dentally erased or overwritten. TheFlash EPROM array may optionallybe populated with Intel 28F640J5a-120 (4M x 16) devices to provide16 MB respectively. Please contactThales Computers for this socketThe board also provides a 32-pinDIP socket for a 27C801 8 Mb(1MB) UVEPROM.

5 The UVEPROMmay be used to store user code oruser data, or to provide the initialboot code for the Flash EPROM andthen be Flash SocketA Compact Flash module can be fit-ted to the onboard plug-in site toprovide up to 1 GB of field-remov-able EEPROMThe board provides a 64 kb serialEEPROM, a Fairchild part#NM24C65U or equivalent, with anIIC interface. The EEPROM hooksdirectly to the PPC405GP/GPr IICbus InterfaceThe board provides 100 Base-TXEthernet, with auto-negotiation to10 Base-T when connected to net-works not capable of 100 Mb/soperation. Ethernet supportthrough the Media Access Control(MAC) layer is provided in thePPC405GP/GPr chip.

6 The PhysicalLayer Device (PHY) and the PhysicalMedium Dependent sub-layer andinterface (PMD) are providedonboard. The connections betweenthe MAC and the PHY conform tothe Medium Independent Interface(MII) supported media is Category 5 Unshielded Twisted Pair cable(UTP), accessed via an RJ-45 con-nector on the front panel (convec-tion-cooled version).The Ethernet port can also go outthe rear of the board for conduc-tion-cooled or special Ethernet media access con-troller of the PPC405GP/GPr is ageneric implementation of theEthernet MAC protocol complyingwith ANSI/IEEE and supplement.

7 Its major fea-tures are:> Dual speed (10/100 Mb/s)CSMA/CD (half-duplex) and full-duplex Ethernet MAC>Independent, large (2 kB) trans-mit and (4 kB) receive FIFOs withprogrammable thresholds to min-imize overruns and underruns> Unicast, multicast, broadcast,and promiscuous address filteringcapabilities>Two 64-bit hash filters for unicastand multicast packets> Automatic retransmission of col-lided packets> Compliance with IEEE packet-based flow con-trol, including self-assembled con-trol pause packet transmittingVCE405 Connectivity Engine The VCE405 Connectivity Engineprovides a flexible off-the-shelfmethod for quickly developing anddeploying cost-conscious high-performance custom low power consumption of thepowerful.

8 IBM PowerPC 405GP/GPrand the ALMA2e PCI/VME bridgemake the VCE405 well-suited tocritical environments such asaerospace or medical Data>>>Support for VLAN tag ID in com-pliance with IEEE standard> VLAN tag insertion or replace-ment for transmit packets is aprogrammable option>Wake on LAN (WOL) handlingPlease ask Thales Computers forsupport of this Asynchronous SerialLinesThe PPC405GP/GPr provides twoasynchronous 16550-compliantEIA-232 serial ports (0 and 1).Port 1 is available on the front paneland on the P2 connector, and port0 is available on the P2 port 1 features a 2-wire inter-face (Tx, Rx, GND) while serial port0 features a full modem interface(Tx, Rx, DCD, CTS, RTS, GND).

9 Quad SynchronousAsynchronous SerialLinesTwo enhanced serial communica-tions controllers (ESCC) from Zilog,Z85230-16 provide synchro-nous/asynchronous serial lines atdata rates up to Onecontroller provides dual independ-ent full-duplex synchronous or asyn-chronous channels with software-selectable EIA-232/422/485transceivers (ports 4 & 5). The other provides dual independ-ent full-duplex asynchronous chan-nels with no handshaking capabilityand with software-selectable EIA-232/422/485 transceivers (ports2 & 3). All four serial lines are avail-able on the software-selectable EIA-232/422/485 ESC controller features:> Dual full-duplex channels> Ability to accommodate a crystaloscillator, baud rate generator,and digital phase-locked loop oneach channel> Multiprotocol format (asynchro-nous, monosynchronous, bisyn-chronous, SDLC/HDLC, SDLC/HDLC loop)> Encodes in the following modes.

10 NRZI, FM0, FM1, andManchester> CRC-16 or CRC-CCITT errordetection> 4-byte transmit FIF0/8-bytereceive FIF0 IIC Bus PortThe PPC405GP/GPr provides aninter-integrated circuit (IIC) businterface which is available to theusers on the IIC bus is a two-wire, bi-direc-tional, open-drain, low-speed serialinterface. The serial clock (IICSCL)and serial data (IICSDA) lines arebidirectional to support multiple busmasters and to mix high- and low-speed devices on the same IIC interface is compliant withPhilips Semiconductor s I2C specifi-cation, dated 1995.