VIC068A VMEbus Interface Controller - transputer

1 VMEbus Interface ControllerVIC068A Cypress Semiconductor Corporation 3901 North First Street San Jose CA 95134 408-943-2600 December 1990 - Revised July 23, 1997 Features Complete VMEbus Interface Controller and arbiter 58 internal registers provide configuration control and status of VMEbus and local operations Drives arbitration, interrupt, address modifier utility, strobe, address lines A07 through A01 and data lines D07 through D00 directly, and provides signals for control logic to drive remaining address and data lines Direct connection to 68xxx family and mappable to non-68xxx processors Complete master/slave capability Supports read, write, write posting, and block trans-fers Accommodates VMEbus timing requirements with internal digital delay line (1 2-clock granularity) Programmable metastability delay Programmable data acquisition delays Provides timeout timers for local bus and VMEbus transactions Interleaved block transfers over VMEbus Acts as DMA master on local bus Programmable burst count, transfer length, and in-terleaved period interval Supports local module-based DMA Arbitration support Supports single-level, priority and round robin arbi-tration Supports fair request option as requester Interrupt support Complete support for the VMEbus interrupts: inter-rupter and interrupt handler Seven local interrupt lines 8-level interrupt priority encode Total of 29 interrupts mapped through the VIC068A Miscellaneous features Refresh option for local DRAM Four broadcast location monitors Four module-specific location monitors Eight interprocessor communications registers PGA or QFP packages Compatible with IEEE Specification 1014, Rev.

2 C Supports RMC operations See the VMEbus Interface Handbook for more informa-tionFunctional DescriptionThe VMEbus Interface Controller ( VIC068A ) is a single chipdesigned to minimize the cost and board area requirementsand to maximize performance of the VMEbus Interface of aVMEbus master/slave module. This can be implemented onVIC068A either an 8-bit, 16-bit, or 32-bit VMEbus system. TheVIC068A performs all VMEbus system Controller functionsplus many others, which simplify the development ofVIC068Aa VMEbus Interface . The VIC068A utilizes patentedon-chip output buffers. These CMOS high-drive buffers pro-vide direct connection to the address and data lines. In addi-tion to these signals, the VIC068A connects directly to the ar-bitration, interrupt, address modifier, utility and strobe are provided which control data direction and latchfunctions needed for a 32-bit VIC068A was developed through the efforts of a consor-tium of board vendors, under the auspices of the VMEbus In-ternational Trade Association (VITA).

3 The VIC068A thus in-sures compatibility between boards designed by ConfigurationsAB CDE FG HJ KL MN PRGNDLD6LD2LA7LA3LA2LA1CS*PAS*DSACK0*HAL T*FC2 SIZ1 BLT*LD5LD3LD0LA5LA4LA0 DSACK1*LBERR*R/W*IPL2*RMC*SIZ0 IRESET*ABEN*LIACKO*IPL1*DEDLK*LD7LD4LA6 GNDVCCDS*RESET*FC1 LBR*SCON*LADOVCCLIRQ2*VCCIPL0*LOCATORPIN CLK64 MLEDILEDOLIRQ5*LIRQ1*LAENASIZ1 LIRQ4*LIRQ3*LADIDDIRUWDENIN*GNDLWDENIN*S WDEN*ASIZ0 LIRQ6*LIRQ7*VCCDENO*ISOBE*SLSEL1*ICFSEL* GNDGNDD06D07 WORD*MWB*SLSEL0*VCCD03D05 FIACK*A01 GNDD00D01D04A02A03A06 BGOUT1*GNDD02A04A05 IRQ1*BGIN2*BGOUT0*BGOUT3*VCCA07 IRQ2*IRQ5*SYSFAIL*IACKIN*GNDGNDVCCBERR*B R2*BBSY*BGIN0*BGIN3*BGOUT2*GNDIRQ3*IRQ6* VCCSYSRESET*IACK*AS*AM2 LWORD*WRITE*DS1*BR1*BR3*BGIN1*SYSCLKIRQ4 *IRQ7*ACFAIL*IACKOUT*DTACK*AM0AM1AM3AM4A M5DS0*BR0*GNDBCLR*GNDPin Grid Array (PGA)Bottom ViewLBG*LD1 VIC068A 1 VIC068A3 Pin Configurations (continued) VIC068A 21 GND120 GND2 GND119 GND3 IPL0*118 LBG*4 IPL1*117 IRESET*5 IPL2*116 SCON*6 VCC115 CLK64M7 LAEN114 ABEN*8 LIAKO*113 LADO9 LIRQ1*112 LADI10 LIRQ2*111 LEDI11 LIRQ3*110 VCC12 LIRQ4*109 LEDO13 LIRQ5*108 DDIR14 LIRQ6*107 UWDENIN*15 LIRQ7*106 GND16 ASIZ1*105 LWDENIN*17 ASIZ0*104 DENO*18 ICFSEL*103 SWDEN*19 SLSEL1*102 ISOBE*20 GND101 VCC21 SLSEL0*100 GND22 WORD*99D0723 FCIACK*98D0624 MWB*97D0525A196D0426 GND95 VCC27A294D0328A393D0229A492D0130 VCC91D0031A590 BGOUT3*32A689 GND33A788 BGOUT2*34 VSS87 BGOUT1*35 IRQ1*86 BGOUT0*36 IRQ2*85 SYSCLK37 IRQ3*84 BGIN3*38 IRQ4*83 BGIN2*39 GND82 GND40 GND81 GND41 VCC160 VCC42 VCC159 VCC43 IRQ5*158 GND44 IRQ6*157 BLT*45 IRQ7*156 DEDLK*46 VCC155LD747 SYSFAIL*154LD648 ACFAIL*153LD549 SYSRESET*152LD450 IACKOUT*151LD351 IACKIN*150LD252 IACK*149LD153 DTACK*148LD054AS*147LA755 GND146LA656AM0145LA557AM1144LA458AM2143L A359AM3142LA260 GND141 GND61 VCC140 VCC62AM4139LA163AM5138LA064 LWORD*137CS*65 WRITE*136 PAS*66 BERR*135DS*67DS0*134 DSACK1*68DS1*133

4 DSACK0*69BR0*132 LBERR*70 GND131 RESET*71BR1*130 HALT*72BR2*129R/W*73BR3*128FC274 BCLR*127FC175 BBSY*126 RMC*76 BGIN0*125 SIZ177 BGIN1*124 SIZ078 GND123 LBR*79 VCC122 VCC80 VCC121 VCC160-Pin Quad Flatpack (QFP)Top Vi ewVIC068A4 Pin Configurations (continued)144-Pin Thin Quad Flatpack (TQFP)Top ViewVIC068A 3 GNDLBG*IRQ5*IPL0*234 IPL1*IRESET*5 IPL2*SCON*6 VCCCLK64M7 LAENABEN*8 LIAKO*LADO9 LIRQ1*LADI10 LIRQ2*LEDI11 LIRQ3*VCC12 LIRQ4*LEDO13 LIRQ5*108 DDIR14 LIRQ6*107 UWDENIN*15 LIRQ7*106 GND16 ASIZ1*105 LWDENIN*17 ASIZ0*104 DENO*18 ICFSEL*103 SWDEN*19 SLSEL1*102 ISOBE*20 GND101 VCC21 SLSEL0*100 GND22 WORD*99D0723 FCIACK*98D0624 MWB*97D0525A196D0426 GND95 VCC27A294D0328A393D0229A492D0130 VCC91D0031A590 BGOUT3*32A689 GND33A788 BGOUT2*34 GND87 BGOUT1*35 IRQ1*86 BGOUT0*36 IRQ2*85 SYSCLKIRQ3*84 BGIN3*IRQ4*83 BGIN2*828141424344 IRQ6*BLT*45 IRQ7*DEDLK*46VC CLD747 SYSFAIL*LD648 ACFAIL*LD549 SYSRESET*LD450 IACKOUT*LD351 IACKIN*LD252 IACK*LD153 DTACK*LD054AS*LA755 GNDLA656AM0LA557AM1LA458AM2143LA359AM314 2LA260 GND141 GND61 VCC140 VCC62AM4139LA163AM5138LA064 LWORD*137CS*65 WRITE*136 PAS*66 BERR*135DS*67DS0*134 DSACK1*68DS1*133 DSACK0*69BR0*132 LBERR*70 VSS131 RESET*71BR1*130 HALT*72BR2*129R/W*123BR3*128FC2122 BCLR*127FC1121 BBSY*126 RMC*120 BGIN0*125 SIZ1119 BGIN1*124 SIZ0118

5 GNDLBR*117116373839408079787776757473115 1141131121111101091441 VIC068A5 VIC068A6 VIC068A on 68030 Board512/256K X 36 DRAM512/256K X 36 DRAMA ddressMuxLatching TransceiversLatching Transceivers680303232 Parity CheckLogic4 JEDEC EPROMsLA0 LA 31D24 D31D16 D23 FCT543A1 A 7 SYSCLKD00 D07AM 0 AM 5AS*, DS0*, DS1*, DTACK*,WRITE*, LWORD*, BERR*BGiIN*, BGiOUT*, BRi*, BBSY*IACK*, IACKIN*, IACKOUT*IRQ1*, IRQ7*, ACFAIL*, SYSFAIL*STSRESET*DDIRVIC068 AFCT543 FCT245 FCT245 FCT245 FCT245 FCT543 FCT543 FCT543 FCT543 Slave Select DecodeLIRQ1* - LIRQ7*LIACKO*SLSEL0*SLSEL1*ICFSELA31 A24A23 16A15 A08W1 DRAM I/OEPROMVMEbusSWDEN*D08 D16 ISOBE*LD0 LD7LA0 LA7 SCON*MWB*WORD*ASIZ1 ASIZ0LD0 LD31 Map DecoderVIC068A 4 VIC068A7 Theory of OperationThe VIC068A is an Interface between a local CPU bus and theVMEbus. The local bus Interface of the VIC068A emulates Mo-torola s family of 32-bit CISC processor interfaces. Other pro-cessors can easily be adapted to Interface to the VIC068 Ausing the appropriate the VIC068 AThe VIC068A can be reset by any of three distinct reset con-ditions:Internal Reset.

6 This reset is the most common means of re-setting the VIC068A . It resets select register values and alllogic within the Reset. This reset provides a means of resetting theVIC068A through the VMEbus backplane. The VIC068A mayalso signal a SYSRESET* by writing a configuration Reset. This provides a complete reset of the reset resets all of the VIC068A s configuration reset should be used with caution since SYSCLK is notdriven while a global reset is in three reset options are implemented in a different mannerand have different effects on the VIC068A configuration VMEbus System ControllerThe VIC068A is capable of operating as the VMEbus systemcontroller. It provides VMEbus arbitration functions, including: Priority, round-robin, and single-level arbitration schemes Driving IACK* Daisy-Chain Driving BGiOUT* Daisy-Chain (All four levels) Driving SYSCLK output VMEbus arbitration timeout timerThe System Controller functions are enabled by the SCON* pinof the VIC068A .

7 When strapped LOW, the VIC068A functionsas the VMEbus system VMEbus Master CyclesThe VIC068A is capable of becoming the VMEbus master inresponse to a request from local resources. In this situation,the local resource requests that a VMEbus transfer is VIC068A makes a request for the VMEbus . When theVMEbus is granted to the VIC068A , it then performs the trans-fer and acknowledges the local resource and the cycle is com-plete. The VIC068A is capable of all four VMEbus request lev-els. The following release modes are supported: Release on request (ROR) Release when done (RWD) Release on clear (ROC) Release under RMC* control Bus capture and hold (BCAP)The VIC068A supports A32, A24, and A16, as well as user-de-fined address Write-PostingThe VIC068A is capable of performing master write-posting(bus decoupling). In this situation, the VIC068A acknowledgesthe local resource immediately after the request to theVIC068A is made, thus freeing the local bus.

8 The VIC068 Alatches the local data to be written and performs the VMEbustransfer without the local resource having to wait for CyclesRead-modify-write cycles and indivisible multiple-address cy-cles (EMACS) are easily performed using the VIC068A . Sig-nificant control is allowed to: Requesting the VMEbus on the assertion of RMC* indepen-dent of MWB* (this prevents any slave access from inter-rupting local indivisible cycles) Stretching the VMEbus AS* Making the above behaviors dependent on the local SIZi signalsDeadlock ConditionIf a master operation is attempted when a slave operation tothe same module is in progress, a deadlock condition has oc-curred. The VIC068A will signal a deadlock condition by as-serting the DEDLK* signal. This should be used by the localresource requesting the VMEbus to try the transfer after theslave access has ConditionIf the VIC068A , while it is VMEbus master, has a slave selectsignaled, a self access is said to have occurred. The VIC068 Awill issue a BERR*, which in turn will cause a LBERR* to VMEbus Slave CyclesThe VIC068A is capable of operating as a VMEbus slave con-troller.

9 The VIC068A contains a highly programmable environ-ment to allow for a wide variety of slave configurations. TheVIC068A allows for: D32, D16, or D8 configuration A32, A24, A16, or user-defined address spaces Programmable block transfer support including: DMA-type block transfer (PAS* and DSACKi* held asserted) non-DMA-type block transfer (toggle PAS* and DSACKi*) No support for block transfer Programmable data acquisition delays Programmable PAS* and DS* timing Restricted slave accesses (supervisory accesses only)When a slave access is required, the VIC068A will request thelocal bus. When local bus mastership is obtained, the VIC068 Awill read or write the data to/from the local resource and assertthe DTACK* signal to complete the Write-PostingThe VIC068A is capable of performing a slave write-post op-eration (bus decoupling). When enabled, the VIC068A latchesthe data to be written and acknowledge the VMEbus (assertsDTACK*) immediately thereafter. This prevents the VMEbusfrom having to wait for local bus Modifier (AM) CodesThe VIC068A encodes and decodes the VMEbus addressmodifier codes.

10 For VMEbus master accesses, the VIC068 Aencodes the appropriate AM codes through the VIC068A FCiand ASIZi signals, as well as the block transfer status. ForVIC068A8slave accesses, the VIC068A decodes the AM codes andchecks the slave select control registers to see if the slaverequest is to be supported with regard to address spaces, su-pervisory accesses, and block transfers. The VIC068A alsosupports user-defined AM codes; that is, the VIC068A can bemade to assert and respond to user-defined AM VMEbus Block TransfersThe VIC068A is capable of both master and slave block trans-fers. The master VIC068A performs a block transfer in one oftwo modes: MOVEM-type Block Transfer Master Block Transfer with Local DMAIn addition to these VMEbus block transfers, the VIC068A isalso capable of performing block transfers from one local re-source to another in a DMA-like fashion. This is referred to asa Module-based DMA VMEbus specification restricts block transfers from cross-ing 256-byte boundaries without toggling the address strobe,in addition to restricting the maximum length of the transfer to256 bytes.