Verilog HDL - icrus.org

1 Verilog HDL 1 bit 5 b 01101 5 d13 5 hd5 b01101 bit (= 2 ) (b = 2 , d = 10 , h = 16 ) 3 binary= 2 decimal = 10 hexadecimal = 16 ( ) [ n 1 : 0 ],[ 0 : n 1 ] :n reg wire reg,wire reg , wire reg wire (assign ) always reg assign wire wire 2 reg [ 3 : 0 ] LED ;reg wire MSB( ) LSB( ) LED (3bit 4bit )LED[3]LED :LED[1]LED[0]LED[2] reg[0:3]LED LED[0] LED[1] LED[2] LED[3] 00010 LED :101 LED :01111111 LED : reg [1:0] A;reg [2:0] LED;LED <= 3 b101;A <= LED[1:0].

2 Reg [7:0] LED;LED <= 8 b11111101;reg [0:4] LED;LED[1] <= 1 b1;1A : 3 2 18bit 8bit 5bit 3bit 0 always sw= { a , b , 1 b1 , btn[0] }asw :1 b1btn[0]b ( )reg [4:0] shift;Always@(posedge CLK)shift <= { shift[3:0] , rx }; clk 00100shift :00000shift[3:0] rx10000shift : 3 = <= wire = (assign ) reg <= ( always ) FPGA / & AND | OR ~ NOT ^ EX-OR NOT & < <= > >= == !

3 = << >> 4 module FPGA input output wire,reg,bit module module ( ) ; endmodule module test( input wireCLK, input reg data, input reg [4:0] address, output wire [7:0] LED ); assign assign (NET) bit = ( ) assign = ; assign A = ( B & C ) | ( D B , C D , E 5 always always (NET) ( Sensitivity List ) always@ (0 1 , 1 0 ) always always posedge ( ) negedge ( ) always@( )begin end always@(posedge CLK)begin if(count == 3 b111) count <= 3 b0.)

4 Count 111(2 ) CLK else count <= count + 3 b1 end (1 ) always@(count)begin case(count) count ( , ) 3'b000:LED<=7'b0000000; 3'b001:LED<=7'b0000001; 3'b010:LED<=7'b0000010; 3'b011:LED<=7'b0000100; 3'b100:LED<=7'b0001000; 3'b101:LED<=7'b0010000; count LED ON/OFF 3'b110:LED<=7'b0100000; 3'b111:LED<=7'b1000000; default:LED=7'b0000000; endcase end 6 ( if ) begin end always if if , else if else if ( 1) else if ( 2) else if ( 3) else always@(posedge CLK or negedge RESET)begin if (RESET == 1 b0) count <= 1 b0.

5 Else if (count == 4 d9) begin CLK RESET count<= 1 b0; flag <= 1 b1 end else count <= count + 4 d1 end end , , 7 ( case ) always case 1 begin end if default case( ) 1 : 2 : 3 : 4 : default : endcase always@(count)begin case(count) 4'b0000.

6 LED<=7'b1111110; //0 4'b0001:LED<=7'b0110000; //1 4'b0010:LED<=7'b1101101; //2 4'b0011:LED<=7'b1111001; //3 4'b0100:LED<=7'b0110011; //4 4'b0101:LED<=7'b1011011; //5 4'b0110:LED<=7'b1011111; //6 4'b0111:LED<=7'b1110000; //7 4'b1000:LED<=7'b1111111; //8 4'b1001:LED<=7'b1111011; //9 default:LED<=7'bx; endcase X end 8 1 LED ( 100 MHz) module test( input wire CLK, output wire LED ); reg [26:0] count; reg T1s; reg toggle; always@(posedge CLK)begin if(count == 27'd99999999) begin count <= 27'd0; T1s <= 1'b1.

7 End else begin count <= count + 27'd1; T1s <= 1'b0; end end always@(posedge T1s)begin toggle <= ~toggle; end assign LED = toggle; endmodule CLK LED LED 9 2 module decoder( input wire A, input wire B, input wire C, output reg[6:0]LED); always@(A,B,C) begin case({A,B,C}) 3'b000:LED=7'b0000000; 3'b001:LED=7'b0000001; 3'b010:LED=7'b0000010; 3'b011:LED=7'b0000100; 3'b100:LED=7'b0001000; 3'b101:LED=7'b0010000.

8 3'b110:LED=7'b0100000; 3'b111:LED=7'b1000000; default:LED=7'bx; endcase end endmodule 3 module chattering_eliminator( input clk, input enable, input i_sw, output o_sw); reg [4:0] shift; always@(posedge clk)begin if(enable == 1'b1) shift <= {shift[3:0], i_sw}; end assign o_sw = endmodule 10 ( ) HDL parameter wire reg #(.)

9 ( )) ( . ( ) , ); filter #(.coefficient(cf1)) I1(.toggle(toggle), .slot_in (slot3_in), .slot_out (slot31_out)); filter #(.coefficient(cf2)) I2(.toggle(toggle), .slot_in (slot3_in), .slot_out (slot32_out)); filter #(.coefficient(cf3)) I3(.toggle(toggle), .slot_in (slot3_in), .slot_out (slot33_out)); 2 wire reg parameter parameter [ ] = ; parameter [19:0] address = 20'h04040; 11 (assign) always if case assign ?

10 If case assign = ( ) ? : ; assign enable = (count == 14'd9999) ? 1 b1 : 1'b0; 1 [ ] [ ] ; parameter [15:0] coefficient [0:50]; reg signed [15:0] memory [0:50]; always@(posedge clk)begin if(count == 4 b1111)begin memory[15] <= 16 h0f0f; memory[2][0]