VerilogA Reference Manual

1 Verilog-A Reference Manual Verilog-A Reference Manual 2 Table of Contents Chapter 1: Introduction .. 6 Analog Modeling .. 6 Hardware Description Languages .. 6 7 7 Conservative Systems .. 8 Natures and 8 Signal Flow 9 Conventions Used in this Document .. 9 Chapter 2: Verilog-A 11 Declaring Modules .. 11 Module 11 Ports .. 12 Describing Analog 13 Branches .. 13 Analog 14 Accessing Net and Branch 14 Indirect branch assignment .. 14 Branch Contribution Statement .. 15 Switch Branches .. 15 Hierarchical Structures .. 17 Module Instance Parameter Value Assignment .. 17 By Order .. 17 By Name .. 18 Paramsets .. 18 Ports 21 Port Assignment .. 21 By Order .. 21 Hierarchical system parameters .. 22 23 User-defined Analog 23 Chapter 3: Lexical Conventions.

2 26 White 26 26 Operators .. 2 Strings .. 2 Numbers .. 2 Integer Numbers .. 2 Real Numbers .. 3 Scale 3 Keywords .. 4 Identifiers .. 4 Escaped Identifiers .. 4 System Tasks and Functions .. 5 Compiler Directives .. 5 Attributes .. 5 Chapter 4: Data Types .. 7 Integer .. 7 Real .. 7 Verilog-A Reference Manual 3 Output variables .. 7 Type 8 Net 8 Ground Declaration .. 9 Implicit 10 Genvar .. 10 Parameters .. 11 Chapter 5: Analog Block Statements .. 15 Sequential Block .. 15 Conditional Statement (if-else) .. 15 Case Statement .. 16 Repeat Statement .. 17 While Statement .. 17 For Statement .. 18 Chapter 6: Mathematical Functions and Operators .. 19 Unary/Binary/Ternary Operators .. 19 Arithmetic Operators .. 19 Relational Operators.

3 20 Logical Operators .. 20 Bit-wise Operators .. 21 Shift Operators .. 22 Conditional (Ternary) Operator .. 22 Precedence .. 23 Concatenation 23 Expression Evaluation .. 24 Arithmetic Conversion .. 24 Mathematical 24 Standard Mathematical Functions .. 24 Transcendental Functions .. 25 Statistical 26 The $random 26 The $dist_uniform and $rdist_uniform 27 The $dist_normal and $rdist_normal 27 The $dist_exponential and $rdist_exponential Functions .. 28 The $dist_poisson and $rdist_poisson 28 The $dist_chi_square and $rdist_chi_square Functions .. 29 The $dist_t and $rdist_t Functions .. 30 The $dist_erlang and $rdist_erlang Functions .. 30 Chapter 7: Analog Operators and Filters .. 32 32 Parameters .. 33 Time Derivative Operator.

4 33 Time Integrator 33 Circular Integrator Operator .. 34 Derivative Operator .. 35 Absolute Delay Operator .. 35 Transition 36 Slew Filter .. 38 Last Crossing Function .. 39 Limited Exponential .. 40 Laplace Transform 40 laplace_zp() .. 40 laplace_zd() .. 41 laplace_np().. 42 Verilog-A Reference Manual 4laplace_nd().. 43 Z-Transform Filters .. 43 zi_zp() .. 44 zi_zd() .. 44 zi_np().. 45 zi_nd().. 46 Chapter 8: Analog Events ..48 Global Events .. 48 The initial_step 48 The final_step Event .. 49 Global Event Return Codes .. 49 Monitored 50 The cross Function .. 50 Above Function .. 51 The timer Function .. 52 Event or Operator .. 53 Event Triggered Statements .. 54 Chapter 9: Verilog-A and the 55 Environment Parameter Functions.

5 55 The temperature 55 The abstime Function .. 55 The realtime Function .. 56 The Thermal Voltage Function .. 56 The Simulator Parameter Function .. 56 Controlling Simulator Actions .. 58 Bounding the Time Step .. 58 Limiting 58 Announcing Discontinuities .. 60 Analysis Dependent Functions .. 61 Analysis 61 AC Stimulus 62 Noise Functions .. 62 White Noise Function .. 63 Flicker Noise Function .. 63 Noise Table Function .. 64 Chapter 10: System Tasks and I/O 65 Interpolation (table model) 65 Table Model Inputs .. 67 Table Data 67 Table Control String .. 68 Table Interpolation 68 Extrapolation Control 69 File Input/Output Operations .. 70 The fopen Function .. 71 The fclose Function .. 71 The fstrobe Function .. 72 The fdisplay Function.

6 72 The fwrite 73 Display Output Operations .. 73 Strobe Function .. 73 Display Function .. 74 Debug Function .. 74 Format Specification .. 74 Simulator Control 75 Verilog-A Reference Manual 5 The $finish Simulator Control The $stop Simulator Control Operation ..76 Chapter 11: The Verilog-A Preprocessor .. 77 Defining Macros .. 77 Including Files .. 78 Conditional Compilation .. 79 Default transition .. 80 Predefined Macros .. 80 Verilog-AMS and Verilog 1364 1995/2001 80 Unsupported 81 The File .. 86 The File .. 91 Verilog-A Module Template .. 93 Analog Operators and 94 Mathematical 96 Transcendental 97 AC Analysis Stimuli .. 97 Noise 97 Analog Events .. 98 Timestep 99 Input/Output Functions .. 100 Simulator Environment Functions.

7 100 Module Hierarchy .. 101 Verilog-A Reference Manual 6 Chapter 1: Introduction This chapter introduces the Verilog-A language and software in terms of its capabilities, benefits, and typical use. Definitions of terms and conventions used in the document are described. Analog Modeling Analog modeling enables designers to capture high-level behavioral descriptions of components in a precise set of mathematical terms. The analog module s relation of input to output can be related by the external parameter description and the mathematical relations between the input and output ports. Analog models give the designer control over the level of abstraction with which to describe the action of the component. This can provide higher levels of complexity to be simulated, allow faster simulation execution speeds, or can hide intellectual property.

8 An analog model should ideally model the characteristics of the behavior as accurately as possible, with the trade off being model complexity, which is usually manifested by reduced execution speed. For electrical models, besides the port relationship of charges and currents, the developer may need to take thermal behavior, physical layout considerations, environment (substrate, wires) interaction, noise, and light, among other things into consideration. Users prefer that the model be coupled to measurable quantities. This provides reassurance in validating the model, but also provides a means to predict future performance as the component is modified. Models often have to work with controlling programs besides the traditional simulator.

9 Optimization, statistical, reliability, and synthesis programs may require other information than which the model developer was expecting. Hardware Description Languages Hardware description languages (HDLs) were developed as a means to provide varying levels of abstraction to designers. Integrated circuits are too complex for an engineer to create by specifying the individual transistors and wires. HDLs allow the performance to be described at a high level and simulation synthesis programs can then take the language and generate the gate level description. Verilog-A Reference Manual 7 Verilog and VHDL are the two dominant languages; this Manual is concerned with the Verilog language. As behavior beyond the digital performance was added, a mixed-signal language was created to manage the interaction between digital and analog signals.

10 A subset of this, Verilog-A, was defined. Verilog-A describes analog behavior only; however, it has functionality to interface to some digital behavior. Verilog-A Verilog-A provides a high-level language to describe the analog behavior of conservative systems. The disciplines and natures of the Verilog-A language enable designers to reflect the potential and flow descriptions of electrical, mechanical, thermal, and other systems. Verilog-A is a procedural language, with constructs similar to C and other languages. It provides simple constructs to describe the model behavior to the simulator program. The model effectively de-couples the description of the model from the simulator. The model creator provides the constitutive relationship of the inputs and outputs, the parameter names and ranges, while the Verilog-A compiler handles the necessary interactions between the model and the simulator.