Versal ACAP Programmable Network on Chip and Integrated ...

1 Versal ACAP ProgrammableNetwork on Chip andIntegrated MemoryController IP Product GuideVivado Design SuitePG313 ( ) November 8, 2021 xilinx is creating an environment where employees, customers, andpartners feel welcome and included. To that end, we re removing non-inclusive language from our products and related collateral. We velaunched an internal initiative to remove language that could excludepeople or reinforce historical biases, including terms embedded in oursoftware and IPs. You may still find examples of non-inclusivelanguage in our older products as we work to make these changes andalign with evolving industry standards. Follow this link for of ContentsChapter 1: IP 4 Chapter 2: Content by Design Programmable Network on Chip 6 DDR Memory 3: NoC of 4: Integrated Memory Controller (DDRMC) 5: Designing with the to the Inter-NoC the AXI the Memory the AXIS 6: NoC and Memory Controller versus SystemC the 100 Chapter 7: NoC Performance ( ) November 8, 2021 ACAP Programmable NoC and Integrated Memory Controller 2 Send FeedbackPerformance Design of Performance 8: Memory Controller Pinout Rules and FutureExpansion Options for Future 9: System Address Decoding and the System Address A: Memory Interface Memory Debug Hardware Manager Memory Debug.

2 206 UART Calibration B: Additional Resources and Legal Read: Important Legal 234PG313 ( ) November 8, 2021 ACAP Programmable NoC and Integrated Memory Controller 3 Send FeedbackChapter 1IP FactsLogiCORE IP Facts TableCore SpecificsSupported Device Family1 Versal ACAPS upported User InterfacesAXI3, AXI4, and AXI4-StreamProvided with CoreDesign FilesRTLE xample DesignN/ATest BenchVerilogConstraints FileXDCS imulation ModelSystemVerilog, SystemCSupported S/W DriverN/ATested Design Flows2 Design EntryVivado IP integratorSimulationFor supported simulators, see the xilinx Design Tools: Release Notes SynthesisSupportRelease Notes and Known IssuesMaster Answer Record: 75764 All Vivado IP Change LogsMaster Vivado IP Change Logs: 72775 xilinx Support web pageNotes:1. For a complete list of supported devices, see the Vivado IP For the supported versions of third-party tools, see the xilinx Design Tools: Release Notes 1: IP FactsPG313 ( ) November 8, 2021 ACAP Programmable NoC and Integrated Memory Controller 4 Send FeedbackChapter 2 OverviewNavigating Content by Design ProcessXilinx documentation is organized around a set of standard design processes to help you findrelevant content for your current development task.

3 All Versal ACAP design process DesignHubs and the Design Flow Assistant materials can be found on the website. Thisdocument covers the following design processes: System and Solution Planning: Identifying the components, performance, I/O, and datatransfer requirements at a system level. Includes application mapping for the solution to PS,PL, and AI Engine. Topics in this document that apply to this design process include: Features Chapter 3: NoC Architecture Quality of Service Performance Metrics Embedded Software Development: Creating the software platform from the hardwareplatform and developing the application code using the embedded CPU. Also covers XRT andGraph APIs. Topics in this document that apply to this design process include: Address Decoding and the System Address Map Chapter 7: NoC Performance Tuning Hardware, IP, and Platform Development: Creating the PL IP blocks for the hardwareplatform, creating PL kernels, functional simulation, and evaluating the Vivado timing,resource use, and power closure.

4 Also involves developing the hardware platform for systemintegration. Topics in this document that apply to this design process include: Chapter 5: Designing with the Core Clocking Resets Address Decoding and the System Address MapChapter 2: OverviewPG313 ( ) November 8, 2021 ACAP Programmable NoC and Integrated Memory Controller 5 Send Feedback Board System Design: Designing a PCB through schematics and board layout. Also involvespower, thermal, and signal integrity considerations. Topics in this document that apply to thisdesign process include: Pinout Rules Pinout Options for Future Expansion Tutorials: The following tutorials provide guidance on Network -on-Chip (NoC) and DDRM emory Design and Optimization: Introduction to NoC/DDRMC Design Flow Introduction to NoC/DDRMC Performance TuningVersal Programmable Network on ChipOverviewThe xilinx Versal Programmable Network on chip (NoC) is an AXI-interconnecting networkused for sharing data between IP endpoints in the Programmable logic (PL), the processingsystem (PS), and other Integrated blocks.

5 This device-wide infrastructure is a high-speed, Integrated data path with dedicated switching. The NoC can be logically configured to representcomplex topologies using a series of horizontal and vertical paths and a set of customizablearchitectural NoC was designed for scalability. It is composed of a series of interconnected horizontal(HNoC) and vertical (VNoC) paths, supported by a set of customizable, hardware implementedcomponents that can be configured in different ways to meet design timing, speed and logicutilization HNoC and VNoC are dedicated, high bandwidth paths connecting Integrated blocksbetween the processor system and the Programmable logic (PL) without consuming largeamounts of Programmable NoC supports end-to-end quality of service (QoS) to effectively manage transactions andbalance competing latency and bandwidth requirements of each traffic NoC components comprise NoC master units (NMU), NoC slave units (NSU), NoC packetswitches (NPS), and NoC Inter-Die-Bridge (NIDB).

6 The NMU is the traffic ingress point; the NSUis the traffic egress point. All IPs have some number of these master and slave connections. TheNIDB connects two super logic regions (SLRs) together, providing high bandwidth between NPS is the crossbar switch, used to fully form the 2: OverviewPG313 ( ) November 8, 2021 ACAP Programmable NoC and Integrated Memory Controller 6 Send FeedbackHorizontal versus Vertical NoCAs shown in the following figure, NoC paths partition into Horizontal NoCs (HNoCs) and VerticalNoCs (VNoCs). The HNoCs are placed on both the bottom and top of the die. There are four bi-directional physical NoC channels in HNoC. While the bottom HNoC has four bi-directionalphysical channels in all devices, in the Prime and AI series devices the top HNoC has only two bi-directional physical channels. The bottom HNoC typically connects to a selection of blocks suchas PS, PMC, CPM, and DDRMC ( Integrated DDR Memory Controller) to list a few.

7 The PS, PMC,and CPM are collectively referred to as Control, Interfaces and Processing System (CIPs). TheHNoC consists of NoC components (NMU, NSU, NPS, and more). Similarly, the top HNoCtypically connects to a selection of blocks such as DDRMC. For SSIT devices, the top HNoCconnects to NoC Inter-Die Bridge (NIDB) providing high bandwidth between two VNoC refers to the vertical NoC column. There are two bi-directional physical NoC channelsin the VNoC. Each Versal device could have more than one VNoC. The VNoC connects to and VNoC are connected to provide a full Network on 1: NoC Block DiagramHNoCProcessor SystemCPM and PMCAI EngineVNoCVNoCPLPLNMUNMUNMUNMUNMUNMUNMUN MUNSUNSUNSUNSUNSUNSUNSUNSUNMUNMUNMUNMUNM UNSUNSUNSUDDRMCNSUNSUNSUNMUNMUNMUNMUNMUN MUNMUNMUNSUNSUNSUNSUNSUNSUNSUNSUNSUDDRMC NSUNSUNSUHNoCNMUNSUNMUNSUX22049-033021 Chapter 2: OverviewPG313 ( ) November 8, 2021 ACAP Programmable NoC and Integrated Memory Controller 7 Send FeedbackDesign capture is achieved using Vivado IP integrator, from where you can specify theinterconnectivity of all of the endpoints.

8 Virtual Channels (VCs) (not shown) can be used toprovide differential quality of service (QoS).FeaturesThe NoC is composed of a series of horizontal (HNoC) and vertical (VNoC) paths, supported by aset of customizable, hardware implemented components that can be configured in different waysto meet design timing, speed, and logic utilization requirements. The following features aresupported: PL to PL communication. PL to CIPS communication. CIPS to PL communication. CIPS to DDR communication. CIPS to AI Engine communication. High bandwidth data transport. Supports standard AXI3 and AXI4 interfaces to the NoC. A soft bridge is required for AXI4-litesupport. Supports clock domain crossing. Internal register programming interconnect for programming NoC registers. Multiple routing options: Based on physical address. Based on destination interface. Virtual address support.

9 Inter-die connectivity with hardened SSIT bridging. Transports bit-stream from source die PMC to PMC in destination die in SSIT configurations. Programmable routing tables for load balancing and deadlock avoidance. Debug and performance analysis features. End-to-end data protection for Reliability, Availability, Serviceability (RAS). Virtual channels and quality of service (QoS) are supported throughout the NoC to effectivelymanage transactions and balance competing latency and bandwidth requirements of eachtraffic stream: Using ingress rate control, the NoC master unit (NMU) can control the injection rate ofpackets into the 2: OverviewPG313 ( ) November 8, 2021 ACAP Programmable NoC and Integrated Memory Controller 8 Send Feedback There are eight virtual channels on each physical link. Each AXI request and responseoccupies a separate Virtual Channel:- Each ingress AXI interface (at NMU) can be statically programmed to select the virtualchannel it maps Virtual channel mapping can be re-programmed (the NMU must be quiesced first).

10 - All AXI QoS values are optionally carried through the NoC. The NoC connection hardware (or access points) use a master-slave, memory mappedconfiguration. The most basic connection over the NoC consists of a single master connectedto a single slave using a single packet switch. Using this approach, the master takes the AXIinformation and packetizes it for transport over the NoC to the slave, via packet switches. Theslave decomposes the packets back to AXI information delivered to the connected back-enddesign. To achieve this, a NoC access point manages all clock domain crossing, switching, anddata buffering between the AXI and NoC side and vice versa. Error-Correcting Code (ECC) is supported for memory mapped transactions (ECC of AXI4-Stream is not supported).The NoC functional blocks are as follows: NoC Master Unit (NMU): Used to connect a master to the NoC. NoC Slave Unit (NSU): Used to connect a slave to the NoC.