Vivado Design Suite User Guide: Synthesis

1 Vivado Design Suite user GuideSynthesisUG901 ( ) June 12, 2019 Synthesis2UG901 ( ) June 12, History The following table shows the revision history for this Summary06/12/2019 Version SynthesisAdded a section describing Incremental Synthesis and how to run it in various 8-1 Updated SystemVerilog constructs and supported UpdatesSyntax and taxonomy and mechanics corrected as Version UpdatesHeadings and labels adjusted for the edits entered as a Block-Level FlowAdded information to the Caution note regarding the BLOCK_SYNTH property, hierarchies.

2 And I/O Shift Register Coding Example Two (VHDL)Corrected a source chapter 16x24-Bit Multiplier Coding Example (Verilog)Replaced a Verilog coding example ConstructsUpdated support statuses of unions and Version UpdatesEditorial updates only. No technical content Version UpdatesMenus and commands renamed for the releaseUsing Synthesis Added a note to the -retiming option. Updated Project Settings Dialog Boxand Strategies AttributesAdded the following attributes: DSP_FOLDING, DSP_FOLDING_FASTCLOCK, and RW_ADDR_COLLISION.

3 Modified the description of CLOCK_BUFFER_TYPE. Added an example: CLOCK_BUFFER_TYPE XDC Example. Added a caution to GATED_CLOCK TRANSLATE_OFF/TRANSLATE_ONAdded xilinx to list of a Block-Level FlowAdded a caution regarding using the BLOCK_SYNTH property. Send FeedbackSynthesis3UG901 ( ) June 12, Dynamic Shift Registers Coding Example (VHDL)Updated code Coding TechniquesUpdated the following code examples: Filename: : : : : : : : : Supported VHDL Overloaded TypesAdded Synopsys to the std_logic_arith statements.

4 Shift Operator ExamplesCorrected srl to sra VHDL Legacy PackagesMoved IEEE Packages to this the syntax of statements in this section. SectionRevision SummarySend FeedbackSynthesis4UG901 ( ) June 12, : Vivado SynthesisIntroduction .. 8 Synthesis Methodology.. 9 Using Synthesis .. 9 Running Synthesis .. 20 Setting a Bottom-Up Out-of-Context Flow.. 24 Incremental Synthesis .. 29 Using Third-Party Synthesis Tools with Vivado IP.. 32 Moving Processes to the Background.. 33 Monitoring the Synthesis Run.

5 34 Following Synthesis .. 34 Analyzing Synthesis Results.. 35 Using the Synthesized Design Environment.. 36 Exploring the Logic.. 37 Running Timing Analysis .. 38 Running Synthesis with Tcl .. 39 Multi-Threading in RTL Synthesis .. 42 Vivado Preconfigured Strategies.. 43 Chapter2: Synthesis AttributesIntroduction .. 45 Supported Attributes.. 45 Custom Attribute Support in Vivado .. 67 Using Synthesis Attributes in XDC files.. 68 Chapter3: Using Block Synthesis StrategiesOverview.. 70 Chapter4: HDL Coding TechniquesIntroduction.

6 74 Advantages of VHDL .. 74 Advantages of Verilog .. 74 Advantages of SystemVerilog .. 75 Flip-Flops, Registers, and Latches.. 75 Latches .. 78 Tristates .. 80 Send FeedbackSynthesis5UG901 ( ) June 12, Registers.. 82 Dynamic Shift Registers.. 86 Multipliers .. 88 Complex Multiplier Examples.. 93 Pre-Adders in the DSP Block .. 96 Using the Squarer in the UltraScale DSP Block .. 98 FIR Filters .. 100 Convergent Rounding (LSB Correction Technique) .. 105 RAM HDL Coding Techniques .. 110 Inferring UltraRAM in Vivado Synthesis .

7 112 RAM HDL Coding Guidelines.. 116 Initializing RAM Contents .. 1513D RAM Inference .. 157 Black Boxes.. 168 FSM Components.. 170 ROM HDL Coding Techniques .. 174 Chapter5: VHDL SupportIntroduction .. 177 Supported and Unsupported VHDL Data Types.. 177 VHDL Objects .. 182 VHDL Entity and Architecture Descriptions .. 183 VHDL Combinatorial Circuits.. 191 Generate Statements.. 192 Combinatorial Processes.. 194 VHDL Sequential Logic.. 198 VHDL Initial Values and Operational Set/Reset.

8 201 VHDL Functions and Procedures.. 202 VHDL Predefined Packages .. 205 Defining Your Own VHDL Packages .. 207 VHDL Constructs Support Status.. 208 VHDL RESERVED Words.. 211 Chapter6: VHDL-2008 Language SupportIntroduction .. 213 Setting up Vivado to use VHDL-2008 .. 213 Supported VHDL-2008 Features .. 214 Send FeedbackSynthesis6UG901 ( ) June 12, : Verilog Language SupportIntroduction .. 226 Verilog Design .. 226 Verilog Functionality .. 227 Verilog Constructs .. 237 Verilog System Tasks and Functions.

9 238 Using Conversion Functions .. 239 Verilog Primitives.. 240 Verilog Reserved Keywords.. 241 Behavioral Verilog .. 242 Modules .. 250 Procedural Assignments .. 252 Tasks and Functions.. 258 Chapter8: SystemVerilog SupportIntroduction .. 267 Targeting SystemVerilog for a Specific File .. 267 Data Types .. 267 Processes .. 271 Procedural Programming Assignments .. 274 Tasks and Functions.. 276 Modules and Hierarchy .. 277 Interfaces .. 278 Packages.. 280 SystemVerilog Constructs.

10 281 Chapter9: Mixed Language SupportIntroduction .. 286 Mixing VHDL and Verilog.. 286 Instantiation.. 287 VHDL and Verilog Libraries .. 289 VHDL and Verilog Boundary Rules .. 289 Binding .. 289 Generics Support .. 290 Port Mapping .. 290 Send FeedbackSynthesis7UG901 ( ) June 12, : Additional Resources and Legal NoticesXilinx Resources.. 291 Solution Centers.. 291 Documentation Navigator and Design Hubs .. 291 References .. 292 Please Read: Important Legal Notices .. 293 Send FeedbackSynthesis8UG901 ( ) June 12, SynthesisIntroductionSynthesis is the process of transforming an RTL-specified Design into a gate-level representation.