VS1053b Datasheet - VLSI

1 VS1053b DatasheetVS1053b -Ogg Vorbis/MP3/AAC/WMA/FLAC/MIDI AUDIO CODEC CIRCUITF eatures DecodesOgg Vorbis;MP3 = MPEG 1 & 2 audio layer III (CBR+VBR +ABR);MP1/MP2 = layers I & II optional;MPEG4 / 2 AAC-LC(+PNS),HE-AAC v2 (Level 3) (SBR + PS);WMA all profiles (5-384 kbps);General MIDI 1 / SP-MIDI format 0 files;FLAC with software plugin;WAV (PCM + IMA ADPCM) Encodes Ogg Vorbis w/ software plugin Encodes stereo IMA ADPCM / PCM Streaming support for MP3 and WAV EarSpeaker Spatial Processing Bass and treble controls Operates with a single MHz clock Can also be used with a MHz clock Internal PLL clock multiplier Low-power operation High-quality on-chip stereo DAC with nophase error between channels Zero-cross detection for smooth volumechange Stereo earphone driver capable of driv-ing a 30 load Quiet power-on and power-off I2S output interface for external DAC Separate voltages for analog, digital.

2 I/O On-chip RAM for user code and data Serial control and data interfaces Can be used as a slave co-processor SPI flash boot for special applications UART for debugging purposes New functions may be added with soft-ware and up to 8 GPIO pins Lead-free RoHS-compliant packageDescriptionVS1053b is an Ogg Vorbis/MP3/AAC/WMA/FLAC/WAVMIDI audio decoder as well as anPCM/IMA ADPCM/Ogg Vorbis encoder on asingle chip. It contains a high-performance,proprietary low-power DSP processor coreVS_DSP4, data memory, 16 KiB instructionRAM and + KiB data RAM for user appli-cations running simultaneously with any built-in decoder, serial control and input data in-terfaces, up to 8 general purpose I/O pins,an UART, as well as a high-quality variable-sample-rate stereo ADC (mic, line, line + micor 2 line) and stereo DAC, followed by anearphone amplifier and a common voltage receives its input bitstream througha serial input bus, which it listens to as asystem slave.

3 The input stream is decodedand passed through a digital volume controlto an 18-bit oversampling, multi-bit, sigma-delta DAC. The decoding is controlled via aserial control bus. In addition to the basic de-coding, it is possible to add application spe-cific features, like DSP effects, to the userRAM factory-programmable unique chipID provides basis for digital rights manage-ment or unit identification : , 2017-11-171VS1053b DatasheetCONTENTSC ontentsVS10531 Table of Contents2 List of Figures51 Licenses62 Disclaimer63 Definitions64 Characteristics & Maximum Ratings.

4 Operating Conditions .. Characteristics .. Consumption .. Characteristics .. Characteristics - Boot Initialization .. 105 Packages and Pin .. 116 Connection Diagram, LQFP-48147 SPI Bus Pin Descriptions .. Native Modes (New Mode, recommended) .. Compatibility Mode (deprecated, do not use in new designs) Request Pin DREQ .. Protocol for Serial Data Interface (SPI / SDI) .. in VS10xx Native Modes (New Mode, recommended) .. Timing Diagram in VS10xx Native Modes (New Mode) .. in VS1001 Compatibility Mode (deprecated, do not use in newdesigns).

5 SDI Mode (deprecated, do not use in new designs) .. Protocol for Serial Command Interface (SPI / SCI) .. Read .. Write .. Multiple Write .. Timing Diagram .. Examples with SM_SDINEW and SM_SDISHARED set .. SCI Writes .. SDI Bytes .. Operation in Middle of Two SDI Bytes .. 258 Supported Audio Decoder MP3 (MPEG layer III) Formats .. MP2 (MPEG layer II) Formats .. 27 Version: , 2017-11-172VS1053b MP1 (MPEG layer I) Formats .. Ogg Vorbis Formats .. AAC (ISO/IEC 13818-7 and ISO/IEC 14496-3) Formats.

6 WMA Formats .. FLAC Formats .. RIFF WAV Formats .. MIDI Formats .. 329 Functional Features .. Flow of VS1053b .. Spatial Processing .. Data Interface (SDI) .. Control Interface (SCI) .. Registers .. (RW) .. (RW) .. (RW) .. (RW) .. (RW) .. (RW) .. (RW) .. (W) .. and SCI_HDAT1 (R) .. SCI_AIADDR (RW) .. SCI_VOL (RW) .. SCI_AICTRL[x] (RW) .. 4810 Clocking .. Hardware Reset .. Software Reset .. Low Power Mode .. Play and Decode.

7 Playing a Whole File .. Cancelling Playback .. Fast Play .. Fast Forward and Rewind without Audio .. Maintaining Correct Decode Time .. Feeding PCM Data .. Ogg Vorbis Recording .. PCM / ADPCM Recording .. Activating PCM / ADPCM Recording Mode .. Reading PCM / IMA ADPCM Data .. Adding a PCM RIFF Header .. Adding an IMA ADPCM RIFF Header .. Playing ADPCM Data .. Sample Rate Considerations .. Record Monitoring Volume .. SPI Boot .. Real-Time MIDI .. 60 Version: , 2017-11-173VS1053b Extra Parameters.

8 Common Parameters .. WMA .. AAC .. Midi .. Ogg Vorbis .. SDI Tests .. Old Sine Test .. New Sine and Sweep Tests .. Pin Test .. SCI Test .. Memory Test .. 6911 VS1053b Who Needs to Read This Chapter .. The Processor Core .. VS1053b Hardware DAC Audio Paths .. VS1053b Hardware ADC Audio Paths .. VS1053b Memory Map .. SCI Hardware Registers .. Serial Data Interface (SDI) Registers .. DAC Registers .. PLL Controller .. GPIO .. Interrupt Control.

9 UART (Universal Asynchronous Receiver/Transmitter) .. UART Registers .. Status UART_STATUS .. Data UART_DATA .. Data High UART_DATAH .. Divider UART_DIV .. UART Interrupts and Operation .. Timers .. Timer Registers .. Configuration TIMER_CONFIG .. Configuration TIMER_ENABLE .. Timer X Startvalue TIMER_Tx[L/H] .. Timer X Counter TIMER_TxCNT[L/H] .. Timer Interrupts .. I2S DAC Interface .. Analog-to-Digital Converter (ADC) .. Resampler SampleRate Converter (SRC) .. Sidestream Sigma-Delta Modulator (SDM).

10 8612 Version Changes Between VS1033c and VS1053a/b Firmware, 2007-03-08 .. 8713 Latest Document Version Changes8914 Contact Information90 Version: , 2017-11-174VS1053b DatasheetLIST OF FIGURESList of Figures1 Pin configuration, LQFP-48.. 112VS1053b in LQFP-48 packaging.. 113 Typical connection diagram using LQFP-48.. 144 SDI in VS10xx Native Mode, single-byte transfer .. 185 SDI in VS10xx Native Mode, multi-byte transfer,X 1.. 186 SDI timing diagram .. 197 SDI in VS1001 Mode - one byte transfer. Do not use in new designs! .. 208 SDI in VS1001 Mode - two byte transfer.