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1 Order this document by mc12040 /D.. The mc12040 is a phase frequency detector intended for use in systems requiring zero phase and frequency difference at lock. In combination with a voltage controlled oscillator (such as the MC1648, MC12147, MC12148 or MC12149), it is useful in a broad range of phase locked loop applications. PHASE FREQUENCY. Operating Frequency = 80 MHz Typical DETECTOR. Pin Conversion Table 14 PIN DIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SEMICONDUCTOR. 20 PIN PLCC 2 3 4 6 8 9 10 12 13 14 16 18 19 20 TECHNICAL DATA. Inputs Outputs R V U D U D. 0 0 X X X X. 14. 0 1 X X X X. 1 1 X X X X 1. 0 1 X X X X P SUFFIX. PLASTIC PACKAGE. 1 1 1 0 0 1. CASE 646. 0 1 1 0 0 1.

2 1 1 1 0 0 1. 1 0 1 0 0 1. 1 1 0 0 1 1. 1 0 0 0 1 1. 1 1 0 1 1 0 19. 8. 1 0 0 1 1 0 3 4. 1 1 0 1 1 0. 0 1 0 1 1 0 FN SUFFIX. 1 1 0 0 1 1 PLASTIC PACKAGE. CASE 775. (PLCC). Not Recommended for New Designs LOGIC DIAGRAM. 4 U (fR>fV). R6 PIN CONNECTIONS. 3 U (fR>fV). R Q. S Compensation 1 14 Vref NC 2 13 NC. Voltage Feedback 3 12 VCC. S NC 4 11 VC. R Q Current Sense 5 10 Output 12 D (fV>fR). V9 NC 6 9 Gnd 11 D (fV>fR) 7 8. RT/CT Power Ground (Top View). VCC1 = Pin 1. VCC2 = Pin 14. VEE = Pin 7. ORDERING INFORMATION. TRUTH TABLE Operating This is not strictly a functional truth table; , it does not cover all possible Device Temperature Range Package modes of operation. However, it gives a sufficient number of tests to ensure that the device will function properly in all modes of operation.

3 MC12040P TA = 0 to +75 C Plastic Motorola, Inc. 1997 Rev 3. mc12040 . ELECTRICAL CHARACTERISTICS. 6 R U 4. The mc12040 has been designed to meet the dc specifications shown in the test table after thermal U 3. equilibrium has been established. Outputs are terminated D 11. through a 50 ohm resistor to + V for + V tests and 9 V. through a 50 ohm resistor to V for V tests. D 12. NOTE: For more information on using an ECL device in a TEST VOLTAGE VALUES. +5V system, refer to Motorola Application Note AN1406/D, Designing with PECL (ECL at + ) (Volts). @ Test Temperature VIHmax VILmin VIHAmin VILAmax VEE. 0 C 25 C Supply Voltage = 75 C mc12040 . TEST VOLTAGE APPLIED TO PINS BELOW.

4 Pi Pin 0 C 25 C 75 C. Under (VCC). Symbol Characteristics Test Min Max Min Max Min Max Unit VIHmax VILmin VIHAmin VILAmax VEE Gnd IE Power Supply Drain 7 120 60 mAdc 7 1,14. IINH Input Current 6 350 Adc 6 7 1,14. 9 350 9 7 1,14. VOH1 Logic 1 3 Vdc Output Voltage 4. 7 1,14. 11. 12. VOL1 Logic 0 3 Vdc Output Voltage 4. 7 1,14. 11. 12. VOHA2 Logic 1 3 Vdc Input Voltage 4. 7 1,14. 11. 12. VOLA2 Logic 0 3 Vdc 9 6. Input Voltage 4 6 9. 7 1,14. 11 9 6. 12 6 9. TEST VOLTAGE VALUES. (Volts). @ Test Temperature VIHmax VILmin VIHAmin VILAmax VEE. 0 C + + + + + 25 C + + + + + Supply Voltage = + 75 C + + + + + mc12040 . TEST VOLTAGE APPLIED TO PINS BELOW. Pin Pi 0 C 25 C 75 C. Under (VCC).

5 Symbol Characteristics Test Min Max Min Max Min Max Unit VIHmax VILmin VIHAmin VILAmax VEE Gnd IE Power Supply Drain 7 115 60 mAdc 1,14 7. IINH Input Current 6 350 Adc 6 1,14 7. 9 350 9 1,14 7. VOH1 Logic 1 3 Vdc Output Voltage 4. 1,14 7. 11. 12. VOL1 Logic 0 3 Vdc Output Voltage 4. 1,14 7. 11. 12. VOHA2 Logic 1 3 Vdc Input Voltage 4. 1,14 7. 11. 12. VOLA2 Logic 0 3 Vdc 9 6. Input Voltage 4 6 9. 1,14 7. 11 9 6. 12 6 9. 2 MOTOROLA RF/IF DEVICE DATA. mc12040 . Figure 1. AC Tests VCC = + To Scope Channel A. F F. 1 14. 4. Pulse 6 U. Gen 1 R. PRF = 3. Duty Cycle = 50% U. t+ = t = Pulse Gen 2 To Scope Channel B. 11. D. 9 V 12. D. 7. F. t t+ VEE = or + Pulse 90%. Gen 1 50%.

6 10%. + 20ns t t+. + NOTES: Pulse 90% 1 All input and output cables to the scope are equal lengths of 50 . Gen 2 50%. 10% coaxial cable . + 2 Unused input and outputs are connected to a 50 resistor to t+ t++ t t+. ground. Output 80%. 50% 3 The device under test must be preconditioned before performing Waveform A 20% the ac tests. Preconditioning may be accomplished by applying pulse generator 1 for a minimum of two pulses prior to pulse gen- t++ t+ t+ t erator 2. The device must be preconditioned again when inputs to Output 80% pins 6 and 9 are interchanged. The same technique applies. Waveform B 50%. 20%. mc12040 TEST VOLTAGES/WAVEFORMS. 0 C 25 C 85 C APPLIED TO PINS LISTED.

7 Pi Pin VEE. Under Output Pulse Pulse or VCC. Symbol Characteristic Test Waveform Max Max Max Unit Gen 1 Gen 2 + t6+4+ Propagation Delay 6,4 B ns 6 9 7 1,14. t6+12+ 6,12 A 9 6. t6+3 6,3 A 6 9. t6+11 6,11 B 9 6. t9+11+ 9,11 B 9 6. t9+3+ 9,3 A 6 9. t9+12 9,12 A 9 6. t9+4 9,4 B 6 9. t3+ Output Rise Time 3 A ns 6 9 7 1,14. t4+ 4 B 6 9. t11+ 11 B 9 6. t14+ 14 A 9 6. t3 Output Fall Time 3 A ns 6 9 7 1,14. t4 4 B 6 9. t11 11 B 9 6. t14 14 A 9 6. MOTOROLA RF/IF DEVICE DATA 3. mc12040 . APPLICATIONS INFORMATION. The mc12040 is a logic network designed for use as a Proper level shifting is accomplished by differentially phase comparator for MECL compatible input signals. It driving the operational amplifier from the normally high determines the lead or lag phase relationship and the time outputs of the phase detector (U and D).

8 Using this technique difference between the leading edges of the waveforms. the quiescent differential voltage to the operational amplifier Since these edges occur only once per cycle, the detector is zero (assuming matched 1 levels from the phase has a range of 2 radians. detector). The U and D outputs are then used to pass along Operation of the device may be illustrated by assuming phase information to the operational amplifier. Phase error two waveforms, R and V (Figure 2), of the same frequency summing is accomplished through resistors R1 connected to but differing in phase. If the logic had established by past the inputs of the operational amplifier. Some R C filtering history that R was leading V, the U output of the detector (pin imbedded within the input network (NO TAG) may be very 4) would produce a positive pulse width equal to the phase beneficial since the very narrow correctional pulses of the difference and the D output (pin 11 ) would simply remain low.

9 mc12040 would not normally be integrated by the amplifier. On the other hand, it is also possible that V was leading R Phase detector gain for this configuration is approximately (Figure 2), giving rise to a positive pulse on the D output and volts/radian. a constant low level on the U output pin. Both outputs for the System phase error stems from input offset voltage in the sample condition are valid since the determination of lead or operational amplifier, mismatching of nominally equal lag is dependent on past edge crossing and initial conditions resistors, and mismatching of phase detector high states at start up. A stable phase locked loop will result from either between the outputs used for threshold setting and phase condition.

10 Measuring. All these effects are reflected in the gain Phase error information is contained in the output duty constant. For example, a 16mV offset voltage in the amplifier cycle that is, the ratio of the output pulse width to total would cause an error of = radian or period. By integrating or low pass filtering the outputs of the degrees of error. Phase error can be trimmed to zero initially detector and shifting the level to accommodate ECL swings, by trimming either input offset or one of the threshold usable analog information for the voltage controlled oscillator resistors (R1 in Figure 3). Phase error over temperature can be developed. A circuit useful for this function is shown in depends on how much the offending parameters drift.