XC1700E, XC1700EL, and XC1700L L Series ... - All …

1 DS027 ( ) June 25, Specification1 Copyright 1998-2008 xilinx , Inc. xilinx , the xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of xilinx in the United States and other countries. All other trademarks are the property of their respective One-time programmable (OTP) read-only memory designed to store configuration bitstreams of xilinx fpgas Simple interface to the FPGA; requires only one user I/O pin Cascadable for storing longer or multiple bitstreams Programmable reset polarity (active High or active Low) for compatibility with different FPGA solutions XC17128E/EL, XC17256E/EL, XC1701, and XC1700L Series support fast configuration Low-power CMOS floating-gate process XC1700E Series are available in 5V and versions XC1700L Series are available in only Available in compact plastic packages.

2 8-pin SOIC, 8-pin VOIC, 8-pin PDIP, 20-pin SOIC, 20-pin PLCC, 44-pin PLCC or 44-pin VQFP Programming support by leading programmer manufacturers Design support using the xilinx Alliance and Foundation software packages Guaranteed 20 year life data retention Lead-free (Pb-free) packaging availableDescriptionThe XC1700 family of configuration PROMs provides an easy-to-use, cost-effective method for storing large xilinx FPGA configuration bitstreams. See Figure 1 for a simplified block the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after the rising clock edge, data appears on the PROM DATA output pin that is connected to the FPGA DIN pin.

3 The FPGA generates the appropriate number of clock pulses to complete the configuration. After configured, it disables the PROM. When the FPGA is in Slave Serial mode, the PROM and the FPGA must both be clocked by an incoming devices can be concatenated by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all PROMs in this chain are interconnected. All devices are compatible and can be cascaded with other members of the device programming, either the xilinx Alliance or Foundation software compiles the FPGA design file into a standard Hex format, which is then transferred to most commercial PROM programmers.

4 <BLXC1700E, XC1700EL, and XC1700 LSeries Configuration PROMsDS027 ( ) June 25, 20088 Product SpecificationRX-Ref Target - Figure 1 Figure 1:Simplified Block Diagram (Does Not Show Programming Circuit)EPROMCellMatrixAddress CounterCEDATAOEO utputCLKVCCVPPGNDDS027_01_021500 TCOERESET/OE/RESETorCEOP roduct Obsolete or Under ObsolescenceXC1700E, XC1700EL, and XC1700L Series Configuration PROMsDS027 ( ) June 25, Specification2 RPin DescriptionDATAData output is in a high-impedance state when either CE or OE are inactive. During programming, the DATA pin is I/O. Note that OE can be programmed to be either active High or active rising edge on the CLK input increments the internal address counter, if both CE and OE are High, this input holds the address counter reset and puts the DATA output in a high-impedance state.

5 The polarity of this input pin is programmable as either RESET/OE or OE/RESET. To avoid confusion, this document describes the pin as RESET/OE, although the opposite polarity is possible on all devices. When RESET is active, the address counter is held at "0", and puts the DATA output in a high-impedance state. The polarity of this input is programmable. The default is active High RESET, but the preferred option is active Low RESET, because it can be driven by the fpgas INIT polarity of this pin is controlled in the programmer interface. This input pin is easily inverted using the xilinx HW-130 Programmer. Third-party programmers have different methods to invert this High, this pin disables the internal address counter, puts the DATA output in a high-impedance state, and forces the device into low-ICC standby Enable output, to be connected to the CE input of the next PROM in the daisy chain.

6 This output is Low when the CE and OE inputs are both active AND the internal address counter has been incremented beyond its Terminal Count (TC) value. In other words: when the PROM has been read, CEO follows CE as long as OE is active. When OE goes inactive, CEO stays High until the PROM is reset. Note that OE can be programmed to be either active High or active voltage. No overshoot above the specified max voltage is permitted on this pin. For normal read operation, this pin must be connected to VCC. Failure to do so may lead to unpredictable, temperature-dependent operation and severe problems in circuit debugging. Do not leave VPP floating!VCC and GNDP ositive supply and ground PinoutsPins not listed are "no connects.

7 ""CapacityPin Name8-pin PDIP (PD8/PDG8)SOIC(SO8/SOG8)VOIC(VO8/VOG8)20 -pin SOIC(SO20)20-pin PLCC(PC20/PCG20)44-pinVQFP(VQ44)44-pin PLCC(PC44)DATA112402 CLK234435 RESET/OE(OE/RESET)386 1319CE41081521 GND5111018, 4124, 3 CEO613142127 VPP71817 3541 VCC82020 3844 DevicesConfiguration BitsXC1704L4,194,304XC1702L2,097,152XC17 01/L1,048,576XC17512L524,288XC1736E36,28 8XC1765E/EL65,536XC17128E/EL131,072XC172 56E/EL262,144 Product Obsolete or Under ObsolescenceXC1700E, XC1700EL, and XC1700L Series Configuration PROMsDS027 ( ) June 25, Specification3 RPinout Diagrams 6 5 4 3 2 1444342414039383736353433323130291819202 1222324252627287891011121314151617PC44 Top ViewNCNCNCNCNCNCNCNCNCNCNCNCRESET/OENCCE NCNCGNDNCNCCEONCNCCLKNCGNDDATA(D0)NCVCCN CNCVPPNCDS027_05_090602 NCNCNCNCNCNCNCNCNCNCNCPD8/PDG8VO8/VOG8SO 8/SOG8 Top ViewDS027_06_060705 VCCVPPCEOGNDDATA(D0)CLKOE/RESETCE8765123 4VQ44 Top ViewNCNCNCNCNCNCNCNCNCNCNCNCRESET/OENCCE NCNCGNDNCNCCEONCNCCLKNCGNDDATA(D0)NCVCCN CNCVPPNCDS027_07_090602 NCNCNCNCNCNCNCNCNCNCNC123456789101144434 2414039383736353433323130292827262524231 213141516171819202122DS027_08_110102SO20 Top ViewVCCNCVPPNCNCNCNCCEONCGND123456789102 0191817161514131211 DATA(D0)

8 NCCLKNCNCNCNCOE/RESETNCCEPC20/PCG20 Top ViewDS027_09_060705321201918171615149101 1121345678 NCDATA(D0)NCVCCNCNCVPPNCNCCEONCGNDNCNCNC CLKNCOE/RESETNCCEP inout Diagrams 6 5 4 3 2 1444342414039383736353433323130291819202 1222324252627287891011121314151617PC44 Top ViewNCNCNCNCNCNCNCNCNCNCNCNCRESET/OENCCE NCNCGNDNCNCCEONCNCCLKNCGNDDATA(D0)NCVCCN CNCVPPNCDS027_05_090602 NCNCNCNCNCNCNCNCNCNCNCPD8/PDG8VO8/VOG8SO 8/SOG8 Top ViewDS027_06_060705 VCCVPPCEOGNDDATA(D0)CLKOE/RESETCE8765123 4VQ44 Top ViewNCNCNCNCNCNCNCNCNCNCNCNCRESET/OENCCE NCNCGNDNCNCCEONCNCCLKNCGNDDATA(D0)NCVCCN CNCVPPNCDS027_07_090602 NCNCNCNCNCNCNCNCNCNCNC123456789101144434 2414039383736353433323130292827262524231 213141516171819202122DS027_08_110102SO20 Top ViewVCCNCVPPNCNCNCNCCEONCGND123456789102 0191817161514131211 DATA(D0)NCCLKNCNCNCNCOE/RESETNCCEPC20/PC G20 Top ViewDS027_09_060705321201918171615149101 1121345678 NCDATA(D0)NCVCCNCNCVPPNCNCCEONCGNDNCNCNC CLKNCOE/RESETNCCEP roduct Obsolete or Under ObsolescenceXC1700E, XC1700EL, and XC1700L Series Configuration PROMsDS027 ( ) June 25, Specification4 RXilinx fpgas and Compatible PROMsControlling PROMsConnecting the FPGA device with the PROM.

9 The DATA output(s) of the of the PROM(s) drives the DIN input of the lead FPGA device. The Master FPGA CCLK output drives the CLK input(s) of the PROM(s). The CEO output of a PROM drives the CE input of the next PROM in a daisy chain (if any). The RESET/OE input of all PROMs is best driven by the INIT output of the lead FPGA device. This connection assures that the PROM address counter is reset before the start of any (re)configuration, even when a reconfiguration is initiated by a VCC glitch. Other methods such as driving RESET/OE from LDC or system reset assume the PROM internal power-on-reset is always in step with the FPGA s internal power-on-reset. This may not be a safe assumption.

10 The PROM CE input can be driven from either the LDC or DONE pins. Using LDC avoids potential contention on the DIN pin. The CE input of the lead (or only) PROM is driven by the DONE output of the lead FPGA device, provided that DONE is not permanently grounded. Otherwise, LDC can be used to drive CE, but must then be unconditionally High during user operation. CE can also be permanently tied Low, but this keeps the DATA output active and causes an unnecessary supply current of 10 mA BitsPROMXC4003E53,984XC17128E(1)XC4005E9 5,008XC17128 EXC4006E119,840XC17128 EXC4008E147,552XC17256 EXC4010E178,144 XC17256 EXC4013E247,968 XC17256 EXC4020E329,312XC1701XC4025E422,176XC170 1XC4002XL61,100XC17128EL(1)