XC95288XL High Performance CPLD - Xilinx

1 DS055 ( April 3, Specification1-800-255-7778 1998-2007 Xilinx , Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without 6 ns pin-to-pin logic delays System frequency up to 208 MHz 288 macrocells with 6,400 usable gates Available in small footprint packages-144-pin TQFP (117 user I/O pins)-208-pin PQFP (168 user I/O pins)-256-pin BGA (192 user I/O pins)-256-pin FBGA (192 user I/O pins)-280-pin CSP (192 user I/O pins))

2 -Pb-free available for all packages Optimized for high- Performance systems-Low power operation-5V tolerant I/O pins accept 5V, , and or output capability-Advanced micron feature size CMOS Fast FLASH technology Advanced system features-In-system programmable-Superior pin-locking and routability with Fast CONNECT II switch matrix-Extra wide 54-input Function Blocks-Up to 90 product-terms per macrocell with individual product-term allocation-Local clock inversion with three global and one product-term clocks-Individual output enable per output pin with local inversion-Input hysteresis on all user and boundary-scan pin inputs-Bus-hold circuitry on all user pin

3 Inputs-Full IEEE Standard boundary-scan (JTAG) Fast concurrent programming Slew rate control on individual outputs Enhanced data security features Excellent quality and reliability -Endurance exceeding 10,000 program/erase cycles-20 year data retention-ESD protection exceeding 2,000V Pin-compatible with 5V-core XC95288 device in the 208-pin HQFP packageWARNING: Programming temperature range of TA = 0 C to +70 CDescriptionThe XC95288XL is a CPLD targeted for high-perfor-mance, low-voltage applications in leading-edge communi-cations and computing systems.

4 It is comprised of 1654V18 Function Blocks, providing 6,400 usable gates withpropagation delays of 6 ns. See Figure 2 for EstimationPower dissipation in CPLDs can vary substantially depend-ing on the system frequency, design application and outputloading. To help reduce power dissipation, each macrocellin a XC9500XL device may be configured for low-powermode (from the default high- Performance mode). In addi-tion, unused product-terms and macrocells are automati-cally deactivated by the software to further conserve a general estimate of ICC, the following equation may beused:ICC(mA) = MCHS( *PTHS + ) + MCLP( *PTLP + ) + * MCTOG(MCHS +MCLP)* fwhere.

5 MCHS = # macrocells in high-speed configurationPTHS = average number of high-speed product terms per macrocellMCLP = # macrocells in low power configurationPTLP = average number of low power product terms per macrocellf = maximum clock frequencyMCTOG = average % of flip-flops toggling per clock (~12%)This calculation was derived from laboratory measurementsof an XC9500XL part filled with 16-bit counters and allowinga single output (the LSB) to be enabled. The actual ICCvalue varies with the design application and should be veri-fied during normal system operation.

6 Figure 1 shows theabove estimation in a graphical form. For a more detaileddiscussion of power consumption in this device, see Xilinx0XC95288XL High Performance CPLDDS055 ( April 3, 200705 Product SpecificationRXC95288XL High Performance ( April 3, 20071-800-255-7778 Product SpecificationRapplication note XAPP114, Understanding XC9500 XLCPLD Power. Figure 1: Typical ICC vs. Frequency for XC95288 XLClock Frequency (MHz)Typical ICC (mA)100200250DS055_01_121501200250300350 4004505005505050150150100094 MHzHighPerformance208 MHzLowPowerXC95288XL High Performance CPLDDS055 ( April 3, Specification1-800-255-7778 RFigure 2.)))

7 XC95288XL Architecture Function Block outputs (indicated by the bold line) drive the I/O Blocks Programming ControllerJTAGC ontrollerI/OBlocksFunctionBlock 1 Macrocells1 to 18 Macrocells1 to 18 JTAG Port354I/O/GTSI/O/GSRI/O/GCKI/OI/OI/OI/O 41I/OI/OI/OI/O3DS055_02_1013001 FunctionBlock 2541818 FunctionBlock 3 Macrocells1 to 18 Macrocells1 to 1854 FunctionBlock 16541818 FunctionBlock 4 Macrocells1 to 185418 Fast CONNECT II Switch MatrixXC95288XL High Performance ( April 3, 20071-800-255-7778 Product SpecificationRAbsolute Maximum Ratings(2)Recommended Operation ConditionsQuality and Reliability CharacteristicsDC Characteristic Over Recommended Operating ConditionsSymbolDescriptionValueUnitsVCC S upply voltage relative to GND to voltage relative to GND(1) to applied to 3-state output(1) to temperature (ambient)(3) 65 to +150oCTJJ unction temperature+150oCNotes: DC undershoot below GND must be limited to either or 10 mA, whichever is easier to achieve.)

8 During transitions, the device pins may undershoot to or overshoot to + , provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. External I/O voltage may not exceed VCCINT by beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website.

9 For Pb-free packages, see voltage for internal logic and input buffersCommercial TA = 0oC to TA = 40oC to + voltage for output drivers for voltage for output drivers for input input voltage0 VCCIOVS ymbolParameterMinMaxUnitsTDRData Retention20-YearsNPEP rogram/Erase Cycles (Endurance)10,000-CyclesVESDE lectrostatic Discharge (ESD)2,000-VoltsSymbolParameterTest ConditionsMinMaxUnitsVOHO utput high voltage for outputsIOH = high voltage for outputsIOH = 500 A90% VCCIO-VVOLO utput low voltage for outputsIOL = low voltage for outputsIOL = 500 leakage currentVCC = Max; VIN = GND or VCC- 10 AIIHI/O high-Z leakage currentVCC = Max; VIN = GND or VCC- 10 AIIHI/O high-Z leakage currentVCC = Max; VCCIO = Max; VIN = GND or 10 AVCC Min < VIN < 50 ACINI/O capacitanceVIN = GND; f = MHz-10pFICCO perating supply current(low power mode, active)VIN = GND, No load.

10 F = MHz85 (Typical)mAXC95288XL High Performance CPLDDS055 ( April 3, Specification1-800-255-7778 RAC CharacteristicsSymbolParameterXC95288XL- 6XC95288XL-7XC95288XL-10 UnitsMinMaxMinMaxMinMaxTPDI/O to output setup time before hold time after GCK0-0-0-nsTCOGCK to output FB internal operating setup time before p-term clock hold time after p-term clock clock output to output to output term OE to output term OE to output to output OP-term S/R to output pulse width (High or Low) preset/reset pulse width (High or Low) clock pulse width (High or Low) 3.)