Xilinx Timing Closure User Guide (UG612)

1 [ Guide Subtitle] [optional] ug612 (v ) October 16, 2012 [optional] Timing Closure user Guide ug612 (v ) October 16, 2012 This document applies to the following software versions: ISE Design Suite through document applies to the following software versions: ISE Design Suite through document applies to the following software versions: ISE Design Suite through document applies to the following software versions: ISE Design Suite through Closure user (v ) October 16, 2012 Notice of DisclaimerThe information disclosed to you hereunder (the Materials ) is provided solely for the selection and use of Xilinx products.

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4 Copyright 2012 Xilinx , Inc. Xilinx , the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owner ug612 (v ) October 16, Closure user GuideRevision HistoryThe following table shows the revision history for this Removed sentence regarding two unrelated clocks. Removed figure Two Unrelated Clocks Entering the FPGA Device Through Separate External Pins and accompanying text. Removed figure Input Clock Goes to a DCM Example and accompanying text.

5 Removed section Two Related Clocks Entering the FPGA Device Through Separate External Pins and accompanying figure. Removed section Period Constraint Syntax. Removed section Asynchronous Design Technique Example. Removed section Constraining Maximum Data Path Delay. Removed section Two Unrelated Clocks Entering Through Separate External Pins. Replaced various references to DCM with DCM/PLL/MMCM. Added sentence The CLOCK_DEDICATED_ROUTE constraint applies to the INSTANCE PIN or NET. Added sentence Setup and hold analysis is done during Timing analysis for Virtex-5 and newer devices.

6 Added new paragraph beginning AREA_GROUP is attached to logical blocks in the design .. Added new paragraph beginning The component switching limit is a device or silicon limit .. 01/18 Moved Timing constraints information from the Constraints Guide (UG625) to this Closure user (v ) October 16, 2012 Timing Closure user (v ) October 16, 2012 Revision History .. 3 Chapter 1: IntroductionChapter 2: Timing Constraint MethodologyBasic Constraints Methodology.. 12 Input Timing Constraints .. 14 Register-To-Register Timing Constraints .. 21 Output Timing Constraints.

7 26 Chapter 3: Timing Constraint PrinciplesConstraint System.. 35 Constraint Priorities.. 57 Timing Constraints .. 60 Period Constraints .. 62 Offset Constraints.. 67 From:To (Multi-Cycle) Constraints .. 73 Grouping Constraint Syntax.. 81 Creating Timing Constraints .. 81 Chapter 4: Specifying Timing Constraints in XSTA pplying XST Timing Constraints .. 83 Timing Model .. 83 XCF Constraint Priority .. 84 Methods for Specifying Timing Constraints in XST.. 84 Syntax Examples for XST Timing Constraints.. 86 Asynchronous Register.. 87 Clock Signal .. 88 Maximum Delay.

8 90 Maximum Skew.. 91 Offset.. 93 Period .. 94 System Jitter .. 97 NET/PIN/INST Timing Ignore .. 99 Timing Group .. 100 Multi-Cycle Path.. 101 Timing Specifications.. 102 Timing Name .. 105 Table of ContentsSend Closure user GuideUG612 (v ) October 16, 2012 Timing Name Net.. 106 Chapter 5: Specifying Timing Constraints in SynplifyConstraint Types.. 108 Specifying Timing Constraints in HDL.. 108 Syntax Examples for HDL Timing Constraints.. 109black_box_pad_pin .. 110black_box_tri_pins.. 111syn_force_seq_prim.. 113syn_gatedclk_clock_en .. 115syn_gatedclk_clock_en_polarity.

9 116syn_isclock .. 118syn_tpdn.. 119syn_tcon .. 121syn_tsun .. 124 Specifying Timing Constraints in an .sdc File (Tcl).. 127define_clock .. 128define_clock_delay.. 130define_compile_point.. 131define_current_design .. 132define_false_path .. 133 define_input_delay.. 135define_io_standard.. 136define_multicycle_path .. 137define_output_delay .. 139define_path_delay .. 141define_reg_input_delay .. 143define_reg_output_delay.. 144 Specify From/To/Through Points .. 145 Specifying Timing Constraints in a SCOPE Spreadsheet.. 149 Forward Annotation.. 149 Chapter 6: Timing AnalysisMulti-Corner, Multi-Node Timing Analysis.

10 151 Asynchronous Reset Paths .. 152 Timing Analyzer.. 152 Timing Report .. 153 Period Analysis .. 154 Clock Domains.. 156 From:To (Multi-Cycle) Analysis .. 164 Offset In Analysis.. 168 Offset In Before Constraint.. 172 Offset In After Constraint .. 180 Send FeedbackTiming Closure user (v ) October 16, 2012 Offset Out Analysis.. 180 Offset Out Constraint .. 183 Offset Out After Constraint .. 184 Offset Out Before Constraint.. 190 Clock Skew .. 191 Clock Uncertainty.. 194 Chapter 7: Achieving Timing ClosureWhen Timing Closure Is Achieved .. 197 Steps to Achieving Timing Closure .