Xilinx UG018 PowerPC 405 Processor Block Reference Guide

1 RPowerPC 405 Processor Block Reference GuideEmbedded Development KitUG018 ( ) January 11, 2010 PowerPC 405 Processor Block Reference ( ) January 11, 2010 Xilinx is disclosing this Specification to you solely for use in the development of designs to operate on Xilinx FPGAs. Except as stated herein, none of the Specification may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx . Any unauthorized use of this Specification may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and does not assume any liability arising out of the application or use of the Specification; nor does Xilinx convey any license under its patents, copyrights, or any rights of others.

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5 Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You represent that use of the Specification in such High-Risk Applications is fully at your risk. 2002 2010 Xilinx , Inc. All rights reserved. Xilinx , the Xilinx logo, and other designated brands included herein are trademarks of Xilinx , Inc. All other trademarks are the property of their respective owners. Revision HistoryThe following table shows the revision history for this Embedded Development Kit (EDK) for EDK release08/20 to include Virtex-4 Updated Ta b l e 2 - 2 4, JTAG Instruction Register length for Virtex-4 devices: FX12, FX40, FX60.

6 Added (Virtex-4 only) DCREMACENABLER output port to Figure 2-29 and Ta b l e B - 1. Added (Virtex-4 only) parity error detection sections for instruction cache, data cache and unified translation lookaside buffer. Introduced new privileged registers (Virtex-4 only) Core Configuration Register 1 (CCR1) and Machine Check Syndrome Register (MCSR). Completely revised PowerPC 405 APU Controller in Chapter 4 including adding descriptions to figures and an entirely new section: Flushed FCM Instructions. UG018 ( ) January 11, 405 Processor Block Reference Guide06/05 Added Virtex-4 FX fractional clock width support in PLB in Chapter 2.

7 Removed figure titled Incorrect Wiring of JTAG Chain with Individual PPC405 Connections in Connecting PPC405 JTAG Logic Directly to Programmable I/O in Chapter 2. Clarified Execution Re-ordering in Chapter 3. On Table 3-5, page 150, clarified DSOCMBRAMEN for Virtex-4 Updated Preface, page 9. Consistent use of the save/restore register acronym (SSR) revised in Table 4-4, page See XCN10007, Removing Support for PowerPC405 Parity Checking in all Virtex-4 FX FPGAs, , for detailed product revisions: Removed parity detection and discussion of the Core Configuration Register for Virtex-4 FPGAs from PowerPC 405 Software Features in Chapter 1.

8 Removed Memory Management Unit Operation (Virtex-4 FPGAs only) section from Memory Management Unit in Chapter 1. Removed Instruction Cache Unit Parity Operation (Virtex-4 FPGAs only) and Data Cache Unit Parity Operation (Virtex-4 FPGAs only) sections from Instruction and Data Caches in Chapter 405 Processor Block Reference ( ) January 11, 2010 PowerPC 405 Processor Block Reference ( ) January 11, 2010 Revision History .. 2 Preface: About This GuideGuide Contents .. 9 Additional Resources .. 10 Conventions .. 10 Typographical .. 10 Online Document .. 11 General Conventions .. 11 Registers.. 12 Terms.. 12 Chapter 1: Introduction to the PowerPC 405 ProcessorPowerPC Architecture.

9 17 PowerPC Embedded-Environment Architecture .. 18 PowerPC 405 Software Features .. 21 Privilege Modes .. 22 Address Translation Modes .. 22 Addressing Modes .. 23 Data Types .. 23 Register Set Summary .. 24 PowerPC 405 Hardware Organization.. 25 Central-Processing Unit .. 27 Exception Handling Logic .. 27 Memory Management Unit .. 27 Instruction and Data Caches .. 28 Timer Resources .. 29 Debug .. 29 PowerPC 405 Interfaces .. 30 PowerPC 405 Performance.. 31 Chapter 2: Input/Output InterfacesSignal Naming Conventions.. 34 Clock and Power Management Interface.. 35 CPM Interface I/O Signal Summary .. 36 CPM Interface I/O Signal Descriptions.

10 37 System Design Considerations for Clock Domains .. 39 CPU Control Interface.. 41 CPU Control Interface I/O Signal Summary .. 41 CPU Control Interface I/O Signal Descriptions .. 42 Reset Interface .. 43 Reset Requirements .. 43 Reset Interface I/O Signal Summary .. 44 Table of 405 Processor Block Reference GuideUG018 ( ) January 11, 2010 RReset Interface I/O Signal Descriptions .. 45 Instruction-Side Processor Local Bus Interface.. 47 Instruction-Side PLB Operation .. 47 Instruction-Side PLB I/O Signal Table .. 50 Instruction-Side PLB Interface I/O Signal Descriptions .. 51 Instruction-Side PLB Interface Timing Diagrams.