Zynq-7000 All Programmable SoC Software …

1 Zynq-7000 All Programmable SoC. Software Developers Guide UG821 ( ) September 30, 2015. Revision History The following table shows the revision history for this document. Date Version Revision 09/30/2015 Removed LibXil SKey and LibXil RSA. Added references to the library locations. 06/24/2015 Updated Appendix B, LibXil SKey for Zynq-7000 AP SoC Devices ( ). Changed Vivado Device Programmer to Vivado hardware manager. Changed Platform Reference Manual reference to Generating Software Platforms (UG1138). Updated Bootgen options to match -h in Vivado Tcl Console in Table A-3.

2 04/01/2015 Added miscellaneous references throughout the document. Updated BIF File Attributes. Added Bootgen Command Options. Updated Partition Attribute Bits. 06/04/2014 Updated Bootgen to remove the -i option in Bootgen Command Options. Throughout document, added cross-references and updated links in Appendix D, Additional Resources and Legal Notices. Added definitions for RSA and SHA-2. Removed reference to UG652. Changed AP to PS on page 23. 04/02/2014 Initial release for Zynq-7000 AP SoC SWDG Send Feedback 2.

3 UG821 ( ) September 30, 2015. Table of Contents Chapter 1: Introduction to Programming with Zynq-7000 AP SoC Devices Overview.. 5. Introduction .. 5. Architectural Decisions .. 6. Operating System (OS) Considerations .. 7. Chapter 2: Software Application Development Flows Introduction .. 9. Software Tools Overview .. 10. Bare-Metal Device Driver Architecture .. 14. Bare-Metal Application Development .. 17. Linux Application Development .. 21. Additional Information .. 26. Chapter 3: Boot and Configuration Overview.

4 27. Boot Modes .. 28. Boot Stages.. 28. Boot Image Creation .. 48. BootROM Header Format .. 51. Chapter 4: Linux Introduction .. 52. Git Server and Gitk Command.. 52. Linux BSP Contents .. 53. U-Boot.. 54. Appendix A: Using Bootgen Introduction .. 55. BIF File Syntax .. 55. Initialization Pairs and the INT File Attribute.. 58. Encryption Overview .. 59. Authentication Overview .. 60. Zynq-7000 AP SoC SWDG Send Feedback 3. UG821 ( ) September 30, 2015. Bootgen Command Options .. 61. Image Header Table .. 63. Partition Header Table.

5 64. Partition Attribute Bits .. 65. Image Header .. 66. Appendix B: Additional Resources and Legal Notices xilinx Resources .. 67. Solution Centers.. 67. References .. 67. Please Read: Important Legal Notices .. 68. Zynq-7000 AP SoC SWDG Send Feedback 4. UG821 ( ) September 30, 2015. Chapter 1. Introduction to Programming with Zynq-7000 AP SoC Devices Overview This document summarizes the Software -centric information required for designing with xilinx Zynq -7000 All Programmable SoC devices. It assumes that you are: Experienced with embedded Software design Familiar with ARM development tools Familiar with xilinx FPGA devices, intellectual property (IP cores), development tools, and tool environments.

6 Introduction The addition of extensibility of the SoC for both hardware and Software programmability imposes new requirements on design flows for both hardware and Software . Certain hardware features are unique to xilinx , such as hardware co-simulation and co-debug functionality that make it possible to verify custom logic implemented on Zynq-7000 AP SoC devices or in a logic simulation environment while applications execute on a Zynq-7000 AP SoC processor on a physical board or an emulator. For a step-by-step explanation on designing a Zynq-based embedded system, see the following documents: Vivado Design Suite Tutorial: Embedded Processor Hardware Design (UG940) [Ref 6].

7 Vivado Design Suite User Guide: Embedded Processor Hardware Design (UG898) [Ref 5]. Vivado Design Suite Tutorial: Zynq-7000 All Programmable SoC Embedded Design (UG1165) [Ref 16]. VIDEO: See Enabling Smarter Systems for quick-take videos on the Zynq-7000 AP SoC devices. Zynq-7000 AP SoC SWDG Send Feedback 5. UG821 ( ) September 30, 2015. Chapter 1: Introduction to Programming with Zynq-7000 AP SoC Devices Architectural Decisions You must make several architectural decisions before beginning embedded development on applications to run on the Zynq-7000 AP SoC.

8 Because the Zynq-7000 AP SoC devices have dual-core ARM Cortex -A9 processors, you must determine whether to use Asymmetric Multiprocessing (AMP) or Symmetric Multiprocessing (SMP). The same decision must be made for all embedded Software projects: which operating system(s) to use (if any). This introduction defines both AMP and SMP, and provides an assessment of the trade-offs and concerns with each method. Multiprocessing Considerations The following subsections describe the two multiprocessing considerations. Asymmetric Multiprocessing Asymmetric multiprocessing (AMP) is a processing model in which each processor in a multiple-processor system executes a different operating system image while sharing the same physical memory.

9 Each image can be of the same operating system, but more typically, each image is a different operating system, complementing the other OS with different characteristics: A full-featured operating system, such as Linux, lets you connect to the outside world through networking and user interfaces. A smaller, light-weight operating system can be more efficient with respect to memory and real-time operations. A typical example is running Linux as the primary operating system along with a smaller, light-weight operating system, such as FreeRTOS or a bare-metal system, which is described in Chapter 4, Linux, as the secondary operating system.

10 The division of system devices (such as the UART, timer-counter, and Ethernet) between the processors is a critical element in system design. In general: Most devices must be dedicated to their assigned processor. The interrupt controller is designed to be shared with multiple processors. One processor is designated as the interrupt controller master because it initializes the interrupt controller. Communication between processors is a key element that allows both operating systems to be effective. It can be achieved in many different ways, including inter-processor interrupts, shared memory, and message passing.