Zynq-7000 SoC Data Sheet: Overview (DS190)

1 DS190 ( ) June 7, Specification1 Copyright 2012 2017 xilinx , Inc., xilinx , the xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of xilinx in the United States and other countries. AMBA, AMBA Designer, ARM, arm cortex -A9, CoreSight, cortex , and PrimeCell are trademarks of ARM in the EU and other countries. PCI, PCIe, and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners. Zynq-7000 All Programmable SoC First Generation ArchitectureThe Zynq -7000 family is based on the xilinx All Programmable SoC architecture. These products integrate a feature-rich dual-core or single-core arm cortex -A9 based processing system (PS) and 28 nm xilinx programmable logic (PL) in a single device. The arm cortex -A9 CPUs are the heart of the PS and also include on-chip memory, external memory interfaces, and a rich set of peripheral connectivity System (PS) arm cortex -A9 Based Application Processor Unit (APU) DMIPS/MHz per CPU CPU frequency.

2 Up to 1 GHz Coherent multiprocessor support ARMv7-A architecture TrustZone security Thumb -2 instruction set Jazelle RCT execution Environment Architecture NEON media-processing engine Single and double precision Vector Floating Point Unit (VFPU) CoreSight and Program Trace Macrocell (PTM) Timer and Interrupts Three watchdog timers One global timer Two triple-timer countersCaches 32 KB Level 1 4-way set-associative instruction and data caches (independent for each CPU) 512 KB 8-way set-associative Level 2 cache(shared between the CPUs) Byte-parity supportOn-Chip Memory On-chip boot ROM 256 KB on-chip RAM (OCM) Byte-parity supportExternal Memory Interfaces Multiprotocol dynamic memory controller 16-bit or 32-bit interfaces to DDR3, DDR3L, DDR2, or LPDDR2 memories ECC support in 16-bit mode 1GB of address space using single rank of 8-, 16-, or 32-bit-wide memories Static memory interfaces 8-bit SRAM data bus with up to 64 MB support Parallel NOR flash support NAND flash support (1-bit ECC) 1-bit SPI, 2-bit SPI, 4-bit SPI (quad-SPI), or two quad-SPI (8-bit) serial NOR flash8-Channel DMA Controller Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and scatter-gather transaction supportI/O Peripherals and Interfaces Two 10/100/1000 tri-speed Ethernet MAC peripherals with IEEE Std and IEEE Std 1588 revision support Scatter-gather DMA capability Recognition of 1588 rev.

3 2 PTP frames GMII, RGMII, and SGMII interfaces Two USB OTG peripherals, each supporting up to 12 Endpoints USB compliant device IP core Supports on-the-go, high-speed, full-speed, and low-speed modes Intel EHCI compliant USB host 8-bit ULPI external PHY interface Two full CAN compliant CAN bus interfaces CAN and CAN and ISO 118981-1 standard compliant External PHY interface Two SD/SDIO compliant controllers Two full-duplex SPI ports with three peripheral chip selects Two high-speed UARTs (up to 1 Mb/s) Two master and slave I2C interfaces GPIO with four 32-bit banks, of which up to 54 bits can be used with the PS I/O (one bank of 32b and one bank of 22b) and up to 64 bits (up to two banks of 32b) connected to the Programmable Logic Up to 54 flexible multiplexed I/O (MIO) for peripheral pin assignmentsInterconnect High-bandwidth connectivity within PS and between PS and PL ARM AMBA AXI based QoS support on critical masters for latency and bandwidth controlZynq-7000 All Programmable SoC data Sheet: OverviewDS190 ( ) June 7, 2017 Product SpecificationZynq-7000 All Programmable SoC data sheet .

4 OverviewDS190 ( ) June 7, Specification2 Programmable Logic (PL)Configurable Logic Blocks (CLB) Look-up tables (LUT) Flip-flops Cascadeable adders36 Kb Block RAM True Dual-Port Up to 72 bits wide Configurable as dual 18 Kb block RAMDSP Blocks 18 x 25 signed multiply 48-bit adder/accumulator 25-bit pre-adderProgrammable I/O Blocks Supports LVCMOS, LVDS, and SSTL to I/O Programmable I/O delay and SerDesJTAG Boundary-Scan IEEE Std Compatible Test InterfacePCI Express Block Supports Root complex and End Point configurations Supports up to Gen2 speeds Supports up to 8 lanesSerial Transceivers Up to 16 receivers and transmitters Supports up to Gb/s data ratesTwo 12-Bit Analog-to-Digital Converters On-chip voltage and temperature sensing Up to 17 external differential input channels One million samples per second maximum conversion rateFeature SummaryTable 1: Zynq-7000 and Zynq-7000S All Programmable SoCsDevice NameZ-7007SZ-7012SZ-7014SZ-7010Z-7015Z-7 020Z-7030Z-7035Z-7045Z-7100 Part NumberXC7Z007 SXC7Z012 SXC7Z014 SXC7Z010XC7Z015XC7Z020XC7Z030XC7Z035XC7Z 045XC7Z100 Processing SystemProcessor CoreSingle-core arm cortex -A9 MPCore with CoreSight Dual-core arm cortex -A9 MPCore with CoreSight Processor ExtensionsNEON & Single / Double Precision Floating Point for each processorMaximum Frequency667 MHz (-1); 766 MHz (-2)667 MHz (-1); 766 MHz (-2); 866 MHz (-3) 667 MHz (-1); 800 MHz (-2).

5 1 GHz (-3)667 MHz (-1) 800 MHz (-2)L1 Cache32 KB Instruction, 32 KB data per processorL2 Cache512 KBOn-Chip Memory256 KBExternal Memory Support(1)DDR3, DDR3L, DDR2, LPDDR2 External Static Memory Support(1)2x Quad-SPI, NAND, NORDMA Channels8 (4 dedicated to Programmable Logic)Peripherals(1)2x UART, 2x CAN , 2x I2C, 2x SPI, 4x 32b GPIOP eripherals w/ built-in DMA(1)2x USB (OTG), 2x Tri-mode Gigabit Ethernet, 2x SD/SDIOS ecurity(2)RSA Authentication, and AES and SHA 256-bit Decryption and Authentication for Secure Boot Processing System to Programmable Logic Interface Ports(Primary Interfaces & Interrupts Only)2x AXI 32b Master 2x AXI 32-bit Slave4x AXI 64-bit/32-bit MemoryAXI 64-bit ACP16 InterruptsZynq-7000 All Programmable SoC data sheet : OverviewDS190 ( ) June 7, Specification3 Programmable LogicXilinx 7 Series Programmable Logic EquivalentArtix -7 FPGAA rtix-7 FPGAA rtix-7 FPGAA rtix-7 FPGAA rtix-7 FPGAA rtix-7 FPGAK intex -7 FPGAK intex-7 FPGAK intex-7 FPGAK intex-7 FPGAP rogrammable Logic Cells23K55K65K28K74K 85K 125K275K 350K 444 KLook-Up Tables (LUTs)14,40034,40040,60017,60046,20053,2 0078,600171,900218,600277,400 Flip-Flops28,80068,80081,20035,20092,400 106,400157,200343,800437,200554,800 Block RAM (# 36 Kb Blocks) Mb(50) Mb(72) Mb(107) Mb(60) Mb(95) Mb (140) Mb (265) Mb (500) Mb (545) Mb (755)DSP Slices (18x25 MACCs)66120170801602204009009002,020 Peak DSP Performance (Symmetric FIR)73 GMACs131 GMACs187 GMACs100 GMACs200 GMACs276 GMACs593 GMACs1,334 GMACs1,334 GMACs2,622 GMACsPCI Express(Root Complex or Endpoint)(3)Gen2 x4 Gen2 x4 Gen2 x4 Gen2 x8 Gen2 x8 Gen2 x8 Analog Mixed Signal (AMS) / XADC2x 12 bit, MSPS ADCs with up to 17 Differential InputsSecurity(2)

6 AES and SHA 256b for Boot Code and Programmable Logic Configuration, Decryption, and AuthenticationNotes: 1. Restrictions apply for CLG225 package. Refer to the UG585, Zynq-7000 AP SoC Technical Reference Manual (TRM) for Security is shared by the Processing System and the Programmable Refer to PG054, 7 Series FPGAs Integrated Block for PCI Express for PCI Express support in specific 1: Zynq-7000 and Zynq-7000S All Programmable SoCs (Cont d)Device NameZ-7007SZ-7012SZ-7014SZ-7010Z-7015Z-7 020Z-7030Z-7035Z-7045Z-7100 Part NumberXC7Z007 SXC7Z012 SXC7Z014 SXC7Z010XC7Z015XC7Z020XC7Z030XC7Z035XC7Z 045XC7Z100 Zynq-7000 All Programmable SoC data sheet : OverviewDS190 ( ) June 7, Specification4 Table 2:Device-Package Combinations: Maximum I/Os and GTP and GTX TransceiversPackage(1)CLG225 CLG400 CLG484 CLG485(2) SBG485(2)Size13 x 13 mm17 x 17 mm19 x 19 mm19 x 19 mm19 x 19 mmBall mmTransceiver Speed (max) Gb/sDevicePS I/O(3)SelectIOPS I/O(3)SelectIOPS I/O(3)SelectIOPS I/O(3)GTPS electIOPS I/O(3)GTXS electIOHR(4)HP(5)HR(4)HP(5)HR(4)HP(5)HR( 4)HP(5)HR(4)HP(5)XC7Z007S8454 128100 XC7Z012S1284150 XC7Z014S128125 128200 XC7Z0108454 128100 XC7Z0151284150 XC7Z020128125 128200 XC7Z030128450100XC7Z035XC7Z045XC7Z100 Notes: 1.

7 All packages listed are Pb-free (SBG485 with exemption 15). Some packages are available with a Pb The Z-7012S and Z-7015 devices in the CLG485 package and the Z-7030 device in the SBG485 package are pin-to-pin PS I/O count does not include dedicated DDR calibration HR = High Range I/O with support for I/O voltage from to HP = High Performance I/O with support for I/O voltage from to 3:Device-Package Combinations: Maximum I/Os and GTP and GTX Transceivers (Cont d)Package(1)FBG484 FBG676 FFG676 FFG900 FFG1156 Size23 x 23 mm27 x 27 mm27 x 27 mm31 x 31 mm35 x 35 mmBall mmTransceiver Speed (max) Gb/sDevicePS I/O(2)GTXS electIOPS I/O(2)GTXS electIOPS I/O(2)GTXS electIOPS I/O(2)GTXS electIOPS I/O(2)GTXS electIOHR(3)HP(4)HR(3)HP(4)HR(3)HP(4)HR( 3)HP(4)HR(3)HP(4)XC7Z007 SXC7Z012 SXC7Z014 SXC7Z010XC7Z015XC7Z020XC7Z03012841006312 841001501284100150XC7Z035128810015012881 0015012816212150XC7Z04512881001501288100 15012816212150XC7Z1001281621215012816250 150 Notes: 1.

8 All packages listed are Pb-free (FBG and FFG with exemption 15). Some packages are available with a Pb PS I/O count does not include dedicated DDR calibration HR = High Range I/O with support for I/O voltage from to HP = High Performance I/O with support for I/O voltage from to All Programmable SoC data sheet : OverviewDS190 ( ) June 7, Specification5 Zynq-7000 Family DescriptionThe Zynq-7000 family offers the flexibility and scalability of an FPGA, while providing performance, power, and ease of use typically associated with ASIC and ASSPs. The range of devices in the Zynq-7000 family allows designers to target cost-sensitive as well as high-performance applications from a single platform using industry-standard tools. While each device in the Zynq-7000 family contains the same PS, the PL and I/O resources vary between the devices. As a result, the Zynq-7000 and Zynq-7000S SoCs are able to serve a wide range of applications including: Automotive driver assistance, driver information, and infotainment Broadcast camera Industrial motor control, industrial networking, and machine vision IP and Smart camera LTE radio and baseband Medical diagnostics and imaging Multifunction printers Video and night vision equipmentThe Zynq-7000 architecture enables implementation of custom logic in the PL and custom software in the PS.

9 It allows for the realization of unique and differentiated system functions. The integration of the PS with the PL allows levels of performance that two-chip solutions ( , an ASSP with an FPGA) cannot match due to their limited I/O bandwidth, latency, and power offers a large number of soft IP for the Zynq-7000 family. Stand-alone and Linux device drivers are available for the peripherals in the PS and the PL. The Vivado Design Suite development environment enables a rapid product development for software, hardware, and systems engineers. Adoption of the ARM-based PS also brings a broad range of third-party tools and IP providers in combination with xilinx s existing PL inclusion of an application processor enables high-level operating system support, , Linux. Other standard operating systems used with the cortex -A9 processor are also available for the Zynq-7000 PS and the PL are on separate power domains, enabling the user of these devices to power down the PL for power management if required.

10 The processors in the PS always boot first, allowing a software centric approach for PL configuration. PL configuration is managed by software running on the CPU, so it boots similar to an All Programmable SoC data sheet : OverviewDS190 ( ) June 7, Specification6 Figure 1 illustrates the functional blocks of the Zynq-7000 architecture. For more information on the functional blocks, see UG585, Zynq-7000 AP SoC Technical Reference Target - Figure 1 Figure 1:Architectural Overview2x USB2x GigE2x SDZynq-7000 All Programmable SoCI/OPeripherals IRQIRQEMIOS electIOResourcesDMA 8 ChannelCoreSight ComponentsProgrammable LogicDAPDevCSWDTDMASync Notes:1) Arrow direction shows control (master to slave)2) data flows in both directions: AXI 32-Bit/64-Bit, AXI 64-Bit, AXI 32-Bit, AHB 32-Bit, APB 32-Bit, Custom3) Dashed line box indicates 2nd processor in dual-core devices ACP256 KSRAMA pplication Processor UnitTTCS ystem-LevelControlRegsGigECANSDSDIOUARTG PIOUARTCANI2 CSRAM/NOR ONFI Processing SystemMemoryInterfaces Q-SPICTRL USBGigEI2 CUSB SDSDIOSPISPIP rogrammable Logic to Memory InterconnectMMUFPU and NEON EngineSnoop Controller, AWDT, TimerGIC32 KBI-Cache arm cortex -A9 CPUARM cortex -A9 CPUMMUFPU and NEON EngineConfigAES/SHAXADC12-Bit ADC MemoryInterfaces 512 KB L2 Cache & ControllerOCM InterconnectDDR2/3, DDR3L,LPDDR2 Controller DS190_01_07291632 KBD-Cache 32 KBI-Cache 32 KBD-Cache MIOC lockGenerationResetCentralInterconnectGe neral-PurposePor tsHigh-Performance PortsZynq-7000 All Programmable SoC data sheet : OverviewDS190 ( ) June 7, Specification7 Processor System DescriptionAs shown in Figure 1, the PS comprises four major blocks.