10GBASE-KR FEC Tutorial - IEEE 802

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IEEE802 Plenary July 200610GBASE-KR FEC tutorial110GBASE-KR FEC Tutorial Andre Szczepanek (TI)Ilango Ganga (Intel)Cathy Liu (LSI logic)Magesh Valliappan (Broadcom)IEEE802 Plenary July 200610GBASE-KR FEC tutorial2Acknowledgements Jim Hamstra (Flextronics) Winston Mok (PMC Sierra) For the OIF CEI-P FEC, & work on DFE error propagation Andrey Belogolovy (Intel) Andrey Ovchinnikov (Intel) For Code selection and simulation Luke Chang (Intel) Fulvio Spagna (Intel) Joe Caroselli (LSI Logic) For TF contributionsIEEE802 Plenary July 200610GBASE-KR FEC tutorial3Agenda Introduction FEC requirements & code selection DFE Error propagation Simulated Performance of the FEC Ease of Implementation ConclusionIEEE802 Plenary July 200610GBASE-KR FEC tutorial4

IEEE802 Plenary July 2006 10GBASE-KR FEC tutorial 13 FEC block format Payload words carry the 10GBASE-R scrambled payload words Tn = Transcode bit carries the state of the 10GBASE-R sync bits for the associated payload word Sync bits are compressed to аsingle bit then scrambled to ensure DC balance 64b/66b sync bits are either 10 or 01 hence can be reconstructed from the T bit

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