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Finite State Machine Design and VHDL Coding Techniques

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10th International Conference onDEVELOPMENT AND APPLICATION SYSTEMS, Suceava, Romania, May 27-29, 2010273Abstract The first part of paper discusses a variety of issues regarding Finite State Machine Design using the hardware description language. vhdl Coding styles and different methodologies are presented. Our study of FSM focuses on the modeling issues such as vhdl Coding style, State encoding schemes and Mealy or Moore machines. Our discussion is limited to the synchronous FSM, in which the transition is controlled by a clock signal and can occur only at the triggering edge of the second part contains a worked example of a model that detects a unique pattern from a serial input data stream and generates a 1 value to output whenever the sequence 10 occurs.

circuit of the machine is a function of the state vector and the inputs. Mealy outputs are a function of the state vector ... Finite State Machine Design and VHDL Coding Techniques Iuliana CHIUCHISAN, Alin Dan POTORAC, Adrian GRAUR "Stefan cel Mare" University of Suceava

  States, Coding, Design, Machine, Circuit, Finite, Vhdl, Finite state machine design and vhdl coding

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