Transcription of VHDL 2 – Combinational Logic Circuits
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VHDL 2 – Combinational Logic Circuits
vhdl 2 Combinational Logic CircuitsReference: Roth/John Text: Chapter 2 Combinational Logic -- Behaviorcan be specified as concurrent signal assignments-- These model concurrent operation of hardware elementsentity Gates is port (a, b,c: in STD_LOGIC; d: out STD_LOGIC); end Gates;architecture behavior of Gates issignal e: STD_LOGIC;begin-- concurrent signal assignment statementse <= (a and b) xor(not c); --synthesize gate-level cktd <= a nor b and (not e); -- in target technologye n d ; Example: SR latch ( Logic equations)entity SRlatchisport (S,R: in std_logic; -- latch inputsQ,QB: out std_logic) ; -- latch outputsend SRlatch;architecture eqnsof SRlatchissignal Qi,QBi: std_logic; -- internal signalsbeginQBi<= S nor Qi; -- Incorrect would be: QB <= S nor Q;Qi <= R nor QBi; -- Incorrect would be: Q <= R nor QB;Q <= Qi; -- drive output Q with internal QiQB <= QBi; -- drive outputQB with internal QBiend;QiQBiCannot reference output signa
(Processes will be covered in more detail in “sequential circuit modeling”) Modeling combinational logic as a process --All signals referenced in process must be in the sensitivity list.
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