High-Speed Layout Guidelines - TI.com
Application Report SCAA082A November 2006 Revised August 2017. High-Speed Layout Guidelines Alexander Weiler, Alexander Pakosta, and Ankur Verma ........................................ ................ Clock Drivers ABSTRACT. This application report addresses High-Speed signals, such as clock signals and their routing, and gives designers a review of the important coherences. With some simple rules, electromagnetic interference problems can be minimized without using complicated formulas and expensive simulation tools. Section 1. gives a short introduction to theory, while Section 2 focuses on practical PCB design rules. Either section can be read independently. Contents 1 Theoretical Overview ........................................ ........................................ ........................ 1. Electromagnetic Interference and Electromagnetic Compatibility ........................................ .... 1.
1.6 Return Current and Loop Areas ... can cause interference through a coupling path and can be affected by interference through the coupling path. The coupling can be: • Capacitive • Inductive • Galvanic • Radiated power Figure 1. Model of Electromagnetic Interference
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