MAX 10 FPGA Development Kit User Guide
MAX 10 FPGA Development Kit UserGuideSubscribeSend Innovation DriveSan Jose, CA 1-1General the 1-4Getting 2-1Quartus II Web Edition the Development 2-1Installing the USB-Blaster 2-2Board Update 2-2Board Test the Configure System Info GPIO 3-7The Flash 3-9The HSMC 3-11The DDR3 3-13The ADC 3-15The HDMI 3-17The Sleep Mode Power 3-20The Clock 4-4Using the Quartus II the Internal Configuration 4-4Switch and Jumper 4-5Status 4-8General user 4-9On-Board 4-10Off-Board Clock 4-11Components and 4-1210/100/1000 Ethernet 4-15HDMI Video 4-16TOC-2Altera 4-17Pmod 4-22USB to 4-24DDR3 Rev.
San Jose, CA 95134 www.altera.com. Contents ... CONNECTOR (J4) FPGA RECONFIGURE BUTTON USER PUSH BUTTONS DC INPUT 12 V (J15) HSMC CONNECTOR (J2) USER LEDs DDR3 64Mx16 SDRAM Enpirion EN2342QI 4A PowerSoC Enpirion EN6337 3A PowerSoC JTAG HEADER (J14) USB BLASTER
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