Transcription of MAX 10 FPGA Development Kit User Guide
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MAX 10 FPGA Development Kit User Guide
MAX 10 FPGA Development Kit UserGuideSubscribeSend Innovation DriveSan Jose, CA 1-1 General the 1-4 Getting 2-1 Quartus II Web Edition the Development 2-1 Installing the USB-Blaster 2-2 Board Update 2-2 Board Test the Configure System Info GPIO 3-7 The Flash 3-9 The HSMC 3-11 The DDR3 3-13 The ADC 3-15 The HDMI 3-17 The Sleep Mode Power 3-20 The Clock 4-4 Using the Quartus II the Internal Configuration 4-4 Switch and Jumper 4-5 Status 4-8 General user 4-9On-Board 4-10 Off-Board Clock 4-11 Components and 4-1210/100/1000 Ethernet 4-15 HDMI Video 4-16 TOC-2 Altera 4-17 Pmod 4-22 USB to 4-24 DDR3 Rev.
San Jose, CA 95134 www.altera.com. Contents ... CONNECTOR (J4) FPGA RECONFIGURE BUTTON USER PUSH BUTTONS DC INPUT 12 V (J15) HSMC CONNECTOR (J2) USER LEDs DDR3 64Mx16 SDRAM Enpirion EN2342QI 4A PowerSoC Enpirion EN6337 3A PowerSoC JTAG HEADER (J14) USB BLASTER
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