MAX 10 FPGA Development Kit User Guide

1 MAX 10 FPGA Development Kit UserGuideSubscribeSend Innovation DriveSan Jose, CA 1-1 General the 1-4 Getting 2-1 Quartus II Web Edition the Development 2-1 Installing the USB-Blaster 2-2 Board Update 2-2 Board Test the Configure System Info GPIO 3-7 The Flash 3-9 The HSMC 3-11 The DDR3 3-13 The ADC 3-15 The HDMI 3-17 The Sleep Mode Power 3-20 The Clock 4-4 Using the Quartus II the Internal Configuration 4-4 Switch and Jumper 4-5 Status 4-8 General user 4-9On-Board 4-10 Off-Board Clock 4-11 Components and 4-1210/100/1000 Ethernet 4-15 HDMI Video 4-16 TOC-2 Altera 4-17 Pmod 4-22 USB to 4-24 DDR3 Rev.

2 B 4-24 DDR3 Rev. C 4-29 Power Distribution 4-31 Additional A-1 user Guide Revision A-1 Compliance and Conformity A-2CE EMI Conformity A-2 TOC-3 Altera FeedbackThe MAX 10 FPGA Development board provides a hardware platform for evaluating the performanceand features of the Intel MAX 10 Development kit includes a RoHS- and CE-compliant MAX 10 FPGA Development board with thefollowing components: Featured Devices: MAX 10 FPGA (10M50D, dual supply, F484 package) Enpirion EN2342QI 4 A PowerSoC Voltage-Mode Synchronous Step-Down Converter withIntegrated Inductor Enpirion EN6337QI 3 A High-Efficiency PowerSoC DC-DC Step-Down Converters with Integrated Inductor Enpirion EP5358xUI 600 mA PowerSoC DC-DC Step-Down Converters with Integrated Inductor MAX II CPLD EPM1270M256C4N (On-board USB-Blaster II) Programming and Configuration: Embedded USB-Blaster II (JTAG) Optional JTAG direct via 10-pin header Memory Devices.

3 64-Mx16 1 Gb DDR3 SDRAM with soft memory controller 128-Mx8 1 Gb DDR3 SDRAM with soft memory controller 512-Mb Quad serial peripheral interface (quad SPI) flash Communication Ports: Two Gigabit Ethernet (GbE) RJ-45 ports Ethernet Port A (Bottom) Ethernet Port B (Top) One UART One high-definition multimedia interface (HDMI) video output One universal high-speed mezzanine card (HSMC) connector Two 12-pin Digilent Pmod compatible connectorsIntel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks ofIntel Corporation or its subsidiaries in the and/or other countries.

4 Intel warrants performance of its FPGA and semiconductor products to currentspecifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expresslyagreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published informationand before placing orders for products or services.

5 *Other names and brands may be claimed as the property of Innovation Drive, San Jose, CA 95134 Analog: Two MAX 10 FPGA analog-to-digital converter (ADC) SMA inputs 2x10 ADC header Potentiometer input to ADC One external 16 bit digital-to-analog converter (DAC) device with SMA output Clocking 25 MHz single-ended, external oscillator clock source Silicon labs clock generator with programmable frequency GUI Mini-USB cable for on-board USB-Blaster II 2A Power Supply and cord Free Quartus II Web Edition design software (download software and license from website)

6 Complete documentation user manual, bill of materials, schematic, and board filesGeneral DescriptionFigure 1-1: MAX 10 FPGA Board Components (Top)PMODCONNECTOR(J4)FPGARECONFIGUREBUT TONUSERPUSH BUTTONSDC INPUT12 V(J15)HSMC CONNECTOR(J2) user LEDsDDR3 64Mx16 SDRAME npirion EN2342QI 4 APowerSoCEnpirion EN6337 3 APowerSoCJTAG HEADER(J14)USB BLASTER(J12)USB to UART(J11)CLOCK GENERATIONCHIPPOT12x10 PIN HEADER(J20)SMA - ANAIN2(J19)HDMI CONNECTOR(J8)FPGA_CPU_RESETBUTTONPOWERSW ITCH(SW3)PMODCONNECTOR(J5)DUAL ETHERNETCONNECTOR(RJ1)SMA - ANAIN1(J18)SMA - DACOUT(J1)16-Bit DACMAX II USB-BLASTER IICIRCUITE thernet A (Bottom)Ethernet B (Top)

7 LED4 LED3 LED2 LED1 LED0 user PB3 user PB2 user PB1 user PB01-2 General CorporationOverviewSend FeedbackFigure 1-2: MAX 10 FPGA Board Components (Bottom)Note:To determine the revision of your board, look for the serial number at the bottom of the 128Mx8 BOARDREVISONSDRAM (U6) user DIP SWITCH(SW2)QUAD SPI FLASHUSER DIP SWITCH(SW1) Description1-3 OverviewAltera CorporationSend FeedbackFigure 1-3: System Block Diagram~HDMI TXUSB Blas terFTDI + MA XII/ VUSB to UARTDC Supp lyDDR 351 2 M b x1 6QS PI Flash1 Gb x1 62x 10 ADC IN/GPI ODACOUTDACAIN1 AIN 2 FPGA _RE SETJTAGQsci llatorPotenti ome terPMO DPMO DHS MC2x 1 GbE~ user DIP SwitchesUser Push ButtonsUser LEDsHandling the BoardWhen handling the board, it is important to observe static discharge :Without proper anti-static handling, the board can be damaged.

8 Therefore, use anti-statichandling precautions when touching the :This Development kit should not be operated in a Vibration the CorporationOverviewSend FeedbackGetting FeedbackQuartus II Web Edition SoftwareThe Quartus II Web Edition Software is a free with no license can download the Web Edition software from the Altera website. Alternatively, you can request Information Quartus II Web Edition Software Altera IP and Software DVD Request FormInstalling the Development the MAX 10 Development Kit installer from the MAX 10 FPGA Development Kit page ofthe Altera website. Alternatively, you can request a Development kit DVD from the Altera Kit Installa tions DVD Request Form page of the Altera the MAX 10 FPGA Development Kit the on-screen instructions to complete the installation process.

9 Be sure that the installationdirectory you choose is in the same relative location to the Quartus II software installation program creates the Development kit directory structure shown in the following :.sof files are used by BTS GUI to configure the MAX 10 device and start correspondingtest. Therefore, do not to move the .sof files from the *\examples\board_test_system Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks ofIntel Corporation or its subsidiaries in the and/or other countries.

10 Intel warrants performance of its FPGA and semiconductor products to currentspecifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expresslyagreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published informationand before placing orders for products or services.