SEMICONDUCTOR MEMORIES

← Back to document page

Digital Integrated Circuits Prentice Hall 1995MemorySEMICONDUCTORMEMORIESDigital Integrated Circuits Prentice Hall 1995MemoryChapter Overview Memory Classification Memory Architectures The Memory Core Periphery ReliabilityDigital Integrated Circuits Prentice Hall 1995MemorySemiconductor MemoryClassificationRWMNVRWMROMEPROME2PR OMFLASHRandomAccessNon-RandomAccessSRAM DRAMMask-ProgrammedProgrammable (PROM)FIFOShift RegisterCAMLIFODigital Integrated Circuits Prentice Hall 1995MemoryMemory Architecture: DecodersWord 0Word 1Word 2Word N-1Word N-2Input-OutputS0S1S2SN-2SN_1(M bits)StorageCellM bitsN WordsWord 0Word 1Word 2Word N-1Word N-2Input-Output(M bits)StorageCellM bitsDecoderA0A1AK-1S0N words => N select signalsToo many select signalsDecoder reduces # of select signalsK = log2NDigital Integrated Circuits Prentice Hall 1995MemoryArray-Structured Memory ArchitectureInput-Output(M bits)Row DecoderAKAK+1AL-12L-KColumn DecoderBit LineWord LineA0AK-1Storage CellSense Amplifiers / : ASPECT RATIO or HEIGHT >> WIDTHAmplify swing torail-to-rail amplitudeSelects appropriat

Semiconductor Memory Classification RWM NVRWM ROM EPROM E2PROM FLASH Random Access Non-Random Access SRAM DRAM Mask-Programmed Programmable (PROM) FIFO Shift Register CAM ... Metal bypass K cells Polysilicon word line WL Polysilicon word line Driver (b) Using a metal bypass (a) Driving the word line from both sides Metal word line WL

  Metal, Semiconductors