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Utmi
Found 2 free book(s)Future Technology Devices International Ltd
www.ftdichip.comUTMI PHY U S B D M USBDP RREF RESET Generator RESET# EST OSCI OSCO 1.8 Volt LDO Regulator VCC 3V3 IN V1.8OUT EEPROM Interface EECS EESK EEDATA PWREN# SUSPEND# 120 MHz Dual Port TX Buffer 4K Bytes Dual Port RX Buffer 4K Bytes Baud Rate Generator MPSSE/ Multi- purpose UART/FIFO Controller ADBUS0 ADBUS1 ADBUS2 …
UTMI+ Low Pin Interface (ULPI) Specification
www.sparkfun.comModify suspend protocol to more closely resemble UTMI. Add SPKR_L and SPKR_MIC to signal list and T&MT connector. Various clarifications. 1.0rc3 January 19, 2004 Specify that PHY must send RX CMD after Reset. Link + PHY clock startup time of no more than 5.6ms for a peripheral is now mandatory. PHY output delay reduced from 10ns to 9ns.