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A Validation Fault Model for Timing …

A Theviolationoftimingconstraintsonsignals withina errors are alsonotdetectedbytraditionaltiminganalys isapproachesbecausetheerrorsmayaffect ,theMis-TimedEvent(MTE)faultmodel, useseveralexamplestoevaluate nottargeted INTRODUCTIONT hewidespread useofcomplex hardware systemsincost-criticalandlife-criticalap plications motivates theneedfora verificationcomplexityhasincreasedto thepointthatit dominatesthecostofdesign. Inorder tomanage thecomplexityoftheproblem,weareinvestiga tingvalidationtechniques,inwhichfunction alityis verifiedbysimulating(oremulating)asystem descriptionwitha giventestinput ,verificationtechniqueshavebeenexploredw hichverify functionalitybyusingformaltechniques( checking,equivalencechecking,automaticth eoremproving)to theadvantagethatthey areprecise,wherevalidationcanonlyprovide a degreeofcertaintywhichislessthan100%.How ever, formaltechniquessufferfromhighcomplexity ,sotheverificationoflargedesignsusingfor maltechniquesaloneis testsequenceofreasonablelength, andthedegreeofcertaintyprovidedcanbecome arbitrarilycloseto100%.

A Validation Fault Model for Timing-InducedFunctional Errors ... Amherst, MA 01003 qzhang@ecs.umass.edu, harris@ecs.umass.edu ... such as VHDL and Verilog, ...

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  Model, Timing, Fault, Errors, Verilog, Umass, Amherst, Fault model for timing, Fault model for timing inducedfunctional errors, Inducedfunctional

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