Transcription of CloCks Understanding clock domain crossing issues
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CloCks Understanding clock domain crossing issues
EE Times-India | December 2007 | Saurabh VermaEngineering ManagerAtrentaAshima S. DabareConsulting Applications EngineerAtrentaIntroductionSoCs are becoming more com-plex these days. A lot of func-tionality is being added to chips and data is frequently transferred from one clock domain to anoth-er. Hence, clock domain crossing verification has become one of the major verification challenges in deep submicron designs. A clock domain crossing occurs whenever data is trans-ferred from a flop driven by one clock to a flop driven by another clock . In Figure 1, signal A is launched by the C1 clock do-main and needs to be captured properly by the C2 clock domain . Depending on the relationship between the two CloCks , there could be different types of prob-lems in transferring data from the source clock to the destina-tion clock .
eetindia.com | December 2007 | EE Times-India domain may not capture it in the very first cycle of the destination clock because of metastability.
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