Transcription of CMOS Comparator Design
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CMOS Comparator Design
Department of Electrical and Computer Engineering Vishal Saxena -1- CMOS Comparator Design Extra Slides Vishal Saxena, Boise State University Vishal Saxena -2- Comparator Design Considerations Comparator = Preamp (optional) + Reference Subtraction (optional for single-bit case) + Regenerative Latch +Static Latch to hold outputs (optional) Design Considerations Accuracy (dynamic and static offset, noise, resolution) Settling time (tracking BW, regeneration speed) Sensitivity/resolution (gain) Metastability (ability to make correct decisions) Overdrive recovery (memory) Power consumption Vishal Saxena -3- An Example CMOS Comparator Vos orginiates from: Preamp input pair mismatch (Vth,W/L) PMOS loads and current mirror Latch offset Charge-Injection clock-feedthru imbalance of the reset switch (M9) Clock routing Parasitics M1M2 ViVosM3M4 VDDM5M6M8M7M9 VSS Vo+Vo-PreampLatch Vishal Saxena -4- Latch Regeneration Exponential regeneration due to positive feedback of M7 and M8 VDDVSSVo PA tracking Latch resetingLatchregenratingVo+Vo-VDDM5M6M8M 7M9 VSS Vo+Vo-CLCL Vishal Saxena -5- Regeneration Speed Linear Model M8M7 CLCLVo+Vo-Vo-Vo+CLgmVo--1 Lmoo/Cgtexp0tV0tV pole RHP single ,/Cgs01/sCgs LmpLm 0VV/sCg111/sCVgVVVooLmLomooo Vishal Saxena -6- Reg.
A fully-differential gain-stage Avoid or use simple CMFB Pre-amp gain reduces input referred offset due to the latch Autozeroing techniques for offset storage and reduction Pre-amp open-loop gain vs tracking bandwidth trade-off Multiple stages of pre-amp limit bandwidth • Optimum value of stages 2-4 §· 00 §·
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