Transcription of CMOS Comparator Design
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Department of Electrical and Computer Engineering Vishal Saxena -1- cmos Comparator Design Extra Slides Vishal Saxena, Boise State University Vishal Saxena -2- Comparator Design Considerations Comparator = Preamp (optional) + Reference Subtraction (optional for single-bit case) + Regenerative Latch +Static Latch to hold outputs (optional) Design Considerations Accuracy (dynamic and static offset, noise, resolution) Settling time (tracking BW, regeneration speed) Sensitivity/resolution (gain) Metastability (ability to make correct decisions) Overdrive recovery (memory) Power consumption Vishal Saxena -3- An Example cmos Comparator Vos orginiates from: Preamp input pair mismatch (Vth,W/L) PMOS loads and current mirror Latch offset Charge-Injection clock-feedthru imbalance of the reset switch (M9) Clock routing Parasitics M1M2 ViVosM3M4 VDDM5M6M8M7M9 VSS Vo+Vo-PreampLatch Vishal Saxena -4- Latch Regeneration Exponential regeneration due to positive feedback of M7 and M8 VDDVSSVo PA tracking Latch resetingLatchregenratingVo+Vo-VDDM5M6M8M 7M9 VSS Vo+Vo-CLCL Vishal Saxena -5- Regeneration Speed Linear Model M8M7 CLCLVo+Vo.
CMOS logic levels •Very fast! •Q+ and Q-are not well defined in reset mode (Φ = 1) •Large short-circuit current in reset mode •Zero DC current after full regeneration •Supply is very noisy M 5 M 6 M 7 Q+ Q-Φ V i + V i-M 1 M 2 M 3 M 4
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