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Computer Architecture: Dataflow (Part I)

Computer Architecture: Dataflow (Part I) Prof. Onur Mutlu Carnegie Mellon University A Note on This Lecture n These slides are from 18-742 Fall 2012, Parallel Computer Architecture, Lecture 22: Dataflow I n Video: n 2 Some Required Dataflow Readings n Dataflow at the ISA level q Dennis and Misunas, A Preliminary Architecture for a Basic data Flow Processor, ISCA 1974. q Arvind and Nikhil, Executing a Program on the MIT Tagged-Token Dataflow Architecture, IEEE TC 1990. n Restricted Dataflow q Patt et al., HPS, a new microarchitecture: rationale and introduction, MICRO 1985. q Patt et al., Critical issues regarding HPS, a high performance microarchitecture, MICRO 1985.

Data Flow ! The models we have examined in 447/740 all assumed " Instructions are fetched and retired in sequential, control flow order ! This is part of the Von-Neumann model of computation " Single program counter " Sequential execution " Control flow determines fetch, execution, commit order What about out-of-order execution?

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