Transcription of Control Flow Graph - Cornell University
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Control Flow Graph - Cornell University
Binary Decision Diagrams(BDDs)ECE 5775 High-Level Digital Design Automation Fall 2022 HW 1 released Lab 1 (CORDIC design) due tomorrow 11:59pm Fixed-point design should not have DSP48 usage1 Announcements Graph algorithms applied to two EDA problems Static timing analysis Binary decision diagrams (BDDs)2 Agenda[source: Alberto Sangiovanni-Vincentelli skeynote at ICCAD 2012] Assumptions: All inputs arrive at time 0 All gate delays = 1ns, wire delay = 0 Clock period = 5ns Question: What is the maximum slowdown of each gate without violating timing?3 More on Static Timing Analysis5-3=25-4=15-5=0 Slacki= RTi ATi5-5=04-4=03-3=02-2=01-1=00-0=00-0=02- 2=04-1=31-1=00-0=03-0=33-0=3 ConeCv:a subgraphrooted on a node v K-feasible cone: #inputs(Cv) K (Can occupy a K-input LUT) K-feasible cut: The set of input nodes of a K-feasible Cv4 FPGA LUT Mapping RevisitedabdfceghAnother 3-feasible cone with an associated cut = {a, b, c}A 3-feasible cone with a cut = {c, e, f}i0i1i2i3i4 Assumptions K=3 All inputs arrive at time 0 Unit delay model: 3-LUT delay = 1; Zero delay on wire Question: Minimum arrival time(AT) of each gate output?
Control Flow Graph (CFG) A control flow graph(CFG), or simply a flow graph, is a directed graph in which: – (i) the nodes are basic blocks; and – (ii) the edges are induced from the possible flow of the program The basic block whose leader is the first intermediate language statement is called the entry node In a CFG we assume no information about data values
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