Vivado HLS Tutorial - Cornell University

VivadoHLS TutorialSteve Dai, Sean Lai, HanchenJin, ZhiruZhangSchool of Electrical and Computer Engineering ECE 5775 High-Level Digital Design Automation Fall 2018 Agenda Logistics and questions Introduction to high-level synthesis C-based synthesis Common HLS optimizations Case study : FIR filter1 What Automateddesign process that transforms a high-level functional specificationtooptimized register-transfer level (RTL)descriptions for efficient hardware implementation Why Productivity lower design complexity and faster simulation speed Portability single source -> multiple implementations Permutability rapid design space exploration -> higher quality of result (QoR)2 High-Level Synthesis (HLS)Permutability: Faster Design Space ExplorationLatencyAreaThroughputUntimedC ombinationalSequentialPipelined++in1+out 1in2in3in4++in1+out1in2in3in4addclk1addc lkAAt1Td3t*3/1==tclk dadd+dsetupT2=1/(3*tclk)A2=Aadd+2*Aregre gaddclk3setupaddclkAAAtTddt*6*3/13+==+++ in+out321432121()in4in3,in2,in1,fout1=in 1+out1in2in3in4 REG3 Control-Data Flow Graph Data type specialization arbitrary-precision fixed-point, custom floating-point Communication/interface specializatio

• lower design complexity and faster simulation speed ... Case Study: Finite Impulse Response (FIR) Filter 14. 15 Finite Impulse Response (FIR) Filter // original, non-optimized version of FIR #define SIZE 128 #define N 10 void fir(int input[SIZE], int output[SIZE]) {// FIR coefficients

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  Study, Simulation, Response, Filter, Impulse, Finite, Of ifrs, Finite impulse response

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