Transcription of Intro to Verilog - MIT
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Intro to Verilog - MIT
Wires Theory vs Reality - Lab 1. Intro to Verilog 30-50mv voltage drop in chip Wires theory vs reality (Lab1) Wires have inductance and resistance Hardware Description Languages power Verilog supply -- structural: modules, instances noise . -- dataflow: continuous assignment .. noise during transitions -- sequential behavior: always blocks -- pitfalls Voltage drop across wires -- other useful features LC ringing after transitions Reminder: Lab #1 due by 9pm tonight Fall 2017 lecture 3 1 Fall 2017 lecture 3 2. Bypass (Decoupling) Capacitors The Need for HDLs Electrolytic Bypass capacitor A specification is an engineering contract that lists all the goals Capacitor 10uf typical for a project: Provides additional filtering from main goals include area, power, throughput, latency, functionality, test power supply coverage, costs (NREs and pi)
6.111 Fall 2017 Lecture 3 6 A Tale of Two HDLs VHDL Verilog ADA-like verbose syntax, lots of redundancy (which can be good!) C-like concise syntax Extensible types and simulation engine. Logic representations are not built in and have evolved with time (IEEE-1164). Built-in types and logic representations. Oddly, this led
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