Introduction to Deep Submicron CMOS Device Technology ...

Slide 1 Loke, Wee & PfiesterAgilent TechnologiesIntroduction to deep Submicron cmos Device Technology & Its Impact on Circuit DesignAlvin Loke, Tin Tin Wee & James R. PfiesterAgilent Technologies, Fort Collins, COIEEE Solid-State Circuits SocietyDecember 8, 2004 Slide 2 Loke, Wee & PfiesterAgilent TechnologiesOutline cmos Technology Trends MOSFET Basics deep Submicron FET Fabrication Sequence Enabling Technologies Second-Order Consequences Dealing with Process Variations in Manufacturing ConclusionsDisclaimer A proper introductionalone would take weeks, let alone a whole semester Need to omit lots of nitty-gritty yet important process details Hopefully, we ll still learn lots of cooldevice physics Slide 3 Loke, Wee & PfiesterAgilent TechnologiesSource: Thompson et al., Intel (2002)Where is cmos Technology Today? Scaling is still alive & well 130nm now standard fare 90nm already in volume manufacturing 65nm integration tough but not insurmountable Some key trends: Aggressive scaling of gate CD (critical dimension) Scaling driven by exclusively by digital circuit needsSource: Wu et al.

Formation of Inversion Layer V T = gate voltage required to reverse doping of silicon surface, i.e., move f s by 2f b onset of inversion (surface is undoped) f b f s M O S f s = 0 onset of strong inversion (V T condition) f ss f b f s V T M O S f s = - b inversion layer V T = V FB + 2f b + Q dep C ox offset bulk drop oxide drop E C E V E i ...

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  Devices, Introduction, Technology, Deep, Formation, Cmos, Introduction to deep submicron cmos device technology, Submicron

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