Lab 3 Layout Using Virtuoso Layout XL (VXL)

1 Lab 3 layout using virtuoso layout xl (VXL) This Lab will go over: 1. Creating Layout with Virtuoso Layout XL (VXL). 2. Transistor Chaining. 3. Creating Standard cell. 4. Manual Routing 5. Providing Substrate or Bulk Connection. 1. Creating Layout with Virtuoso Layout XL (VXL) We will be Using PCELLs developed by NCSU to Layout a 2 inputs nand gate, denoted as nand2. If you are not running CDS tools, do so according to Lab 1. First we need to create a Layout view of our nand2. Go to the library manager and execute (LM)File>New>Cell A pop-up like Figure 1 should appear. Fill out the pop-up exactly as in Figure 1, then click OK. The Virtuoso Layout editor (VLE) will open as shown in Figure 2. Figure 1: Creating Layout view of nand2 2 Figure 2: Virtuoso Layout Editor (VLE) 3 Figure 3: LSW The Layer Select Window (LSW) will also open as shown in Figure 3.

1 Lab 3 Layout Using Virtuoso Layout XL (VXL) This Lab will go over: 1. Creating layout with Virtuoso layout XL (VXL). 2. Transistor Chaining.

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