Transcription of Layout Dependent Proximity Effects in CMOS
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Layout Dependent Proximity Effects in CMOS
Layout - Dependent Proximity Effectsin Deep Nanoscale CMOSJohn Faricelli April 16, 20092 April 16, 2009 AcknowledgementsThis work is the result of the combined effort of many people at AMD and Alvin Loke, James Pattison, Greg Constant, Kalyana Kumar, Kevin Carrejo, Joe Meier, Yuri Apanovich, Victor Andrade, Bill Gardiol, Steve HejlGLOBALFOUNDRIES Akif Sultan, Sushant Suryagandh, Hans VanMeer, Kaveri Mathur, Rasit Topologlu, Uwe Hahn, Thorsten Knopp, Sean Hannon, Darin Chan, Ali Icel, David Wu3 April 16, 2009 Outline Layout - Dependent Proximity Effects Modeling philosophy CAD tools Mitigation of Layout - Dependent stress effects4 April 16, 2009 Nanoscaled CMOS devices are so close to each other that they begin to Proximity effectsHey! Your wellimplant is messingup my threshold voltage!5 April 16, 2009 Proximity Effects can de-rate FET current by 10% (or more), or shift threshold by several 10 s of mV. De-rating factors can only be calculated after Layout extraction, , ignoredin schematic-extracted netlists.
15 April 16, 2009. Stress memorization (NMOS) Source: Chan, IBM (CICC 2005). I. on (µA/µm) I. off (A/µm) 600. 800. 1000. 1200. 10-9. 10-8. 10-7. 10-6. 10-5 ...
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