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LOW VOLTAGE ANALOG CIRCUITS USING STANDARD cmos TECHNOLOGY Phillip E. Allen, Benjamin J. Blalock, and Gabriel A. Rincon School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta, GA 30332-0250 INTRODUCTION There are many factors that are driving the need to have lower power supply voltages in cmos integrated CIRCUITS . As the channel lengths of cmos technology decrease, the maximum allowable VOLTAGE will decrease. Also, as more components are included in the same area on integrated CIRCUITS , the power dissipation increases. Finally, the requirement for portable electronics implies battery operation which favors low VOLTAGE and low power CIRCUITS . These factors and others have caused many to suggest that future implementation of mixed ANALOG digital CIRCUITS USING standard cmos will have power supplies of or less [1-2].
Next, circuit methods of using existing CMOS technology will be described that permit analog circuit operation at low voltages. Each of these methods alone cannot solve the problem but together they offer attractive solutions. One of these methods which is unique with this paper is the channel JFET and its operation and characterization are …
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