Transcription of MSP430x1xx Family User's Guide (Rev. F) - TI.com
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MSP430x1xx Family User's Guide (Rev. F) - TI.com
2006 Mixed Signal ProductsUser s GuideSLAU049F1 SLAZ671A April 2015 Revised December 2016 Submit Documentation FeedbackCopyright 2015 2016, texas instruments IncorporatedCorrections to MSP430x1xx Family User's Guide (SLAU049)Manual Update SheetSLAZ671A April 2015 Revised December 2016 Corrections to MSP430x1xx Family User's Guide (SLAU049)Document Being Updated: MSP430x1xx Family User's GuideLiterature Number Being Updated: SLAU049 FPageChange or Add146 (5-20) InFCTL3, Flash Memory Control Register FCTL3, the BUSY bit is shown as "r(w) 0". Thecorrect value is "r 0".562 (19-12) The following note should be added at the end of theIrDA Decodingsection:NOTE: Reliable reception of IrDA signalsTo receive incoming IrDA signals reliably, make sure that at least one of thefollowing procedures are implemented: Enable the digital filter stage with UCIRRXFE = 1.
Related Documentation From Texas Instruments iii Preface About This Manual This manual discusses modules and peripherals of the MSP430x1xx family of
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